SPRUJ42 User guide | 德州仪器 TI.com.cn

SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1

PRODUCTION DATA

5.15.2.22 MMC_IE Register

15.2.22.1 MMC_IE Register (Offset = 234h) [reset = 0h]

Interrupt Status Enable Register

This register allows to enable/disable the module to set status bits, on an event-by-event basis.

MMCHS_IE[31:16] = Error Interrupt Status Enable
MMCHS_IE[15:0] = Normal Interrupt Status Enable.

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Table 5-1806 Instance Table

Instance Name	Physical Address
MMCSD0	4830 0234h

Figure 5-891 MMC_IE Name Register

31	30	29	28	27	26	25	24
RESERVED3		BADA_ENABLE	CERR_ENABLE	RESERVED2	TE_ENABLE	ADMAE_ENABLE	ACE_ENABLE
R		R/W	R/W	R	R/W	R/W	R/W
0h		0h	0h	0h	0h	0h	0h
23	22	21	20	19	18	17	16
CLE	DEB_ENABLE	DCRC_ENABLE	DTO_ENABLE	CIE_ENABLE	CEB_ENABLE	CCRC_ENABLE	CTO_ENABLE
R	R/W	R/W	R/W	R/W	R/W	R/W	R/W
0h	0h	0h	0h	0h	0h	0h	0h
15	14	13	12	11	10	9	8
NULL	RESERVED				BSR_ENABLE	OBI_ENABLE	CIRQ_ENABLE
R	R				R/W	R/W	R/W
0h	0h				0h	0h	0h
7	6	5	4	3	2	1	0
CREM_ENABLE	CINS_ENABLE	BRR_ENABLE	BWR_ENABLE	DMA_ENABLE	BGE_ENABLE	TC_ENABLE	CC_ENABLE
R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
0h	0h	0h	0h	0h	0h	0h	0h

Table 5-1807 MMC_IE Register Field Descriptions

Bit	Field	Type	Reset	Description
31:30	RESERVED3	R	0h
29	BADA_ENABLE	R/W	0h	Bad access to data space Status Enable 1 Enabled 0 Masked
28	CERR_ENABLE	R/W	0h	Card Error Status Enable 1 Enabled 0 Masked
27	RESERVED2	R	0h
26	TE_ENABLE	R/W	0h	Tuning Error Status Enable 1 Enabled 0 Masked
25	ADMAE_ENABLE	R/W	0h	ADMA Error Status Enable 1 Enabled 0 Masked
24	ACE_ENABLE	R/W	0h	Auto CMD Error Status Enable 1 Enabled 0 Masked
23	CLE	R	0h	Reserved bit. Current limit error is not supported. These bits are initialized to zero, and writes to them are ignored.
22	DEB_ENABLE	R/W	0h	Data End Bit Error Status Enable 1 Enabled 0 Masked
21	DCRC_ENABLE	R/W	0h	Data CRC Error Status Enable 1 Enabled 0 Masked
20	DTO_ENABLE	R/W	0h	Data Timeout Error Status Enable 1 The data timeout detection is enabled. 0 The data timeout detection is deactivated. The host controller provides the clock to the card until the card sends the data or the transfer is aborted.
19	CIE_ENABLE	R/W	0h	Command Index Error Status Enable 1 Enabled 0 Masked
18	CEB_ENABLE	R/W	0h	Command End Bit Error Status Enable 1 Enabled 0 Masked
17	CCRC_ENABLE	R/W	0h	Command CRC Error Status Enable 1 Enabled 0 Masked
16	CTO_ENABLE	R/W	0h	Command Timeout Error Status Enable 1 Enabled 0 Masked
15	NULL	R	0h	Fixed to 0 The host driver shall control error interrupts using the Error Interrupt Signal Enable register. Writes to this bit are ignored
14:11	RESERVED	R	0h
10	BSR_ENABLE	R/W	0h	Boot Status Enable A write to this register when MMCSD_CON[BOOT_ACK] is set to 0x0 is ignored. 1 Enabled 0 Masked
9	OBI_ENABLE	R/W	0h	Out-of-Band Status Enable A write to this register when MMCSD_CON[OBIE] is set to '0' is ignored. 1 Enabled 0 Masked
8	CIRQ_ENABLE	R/W	0h	Card Status Enable A clear of this bit also clears the corresponding status bit. During 1-bit mode, if the interrupt routine doesn't remove the source of a card interrupt in the SDIO card, the status bit is reasserted when this bit is set to 1. 1 Enabled 0 Masked
7	CREM_ENABLE	R/W	0h	Card Removal Status Enable 1 Enabled 0 Masked
6	CINS_ENABLE	R/W	0h	Card Insertion Status Enable 1 Enabled 0 Masked
5	BRR_ENABLE	R/W	0h	Buffer Read Ready Status Enable 1 Enabled 0 Masked
4	BWR_ENABLE	R/W	0h	Buffer Write Ready Status Enable 1 Enabled 0 Masked
3	DMA_ENABLE	R/W	0h	DMA Status Enable 1 Enabled 0 Masked
2	BGE_ENABLE	R/W	0h	Block Gap Event Status Enable 1 Enabled 0 Masked
1	TC_ENABLE	R/W	0h	Transfer Complete Status Enable 1 Enabled 0 Masked
0	CC_ENABLE	R/W	0h	Command Complete Status Enable 1 Enabled 0 Masked