SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1
PRODUCTION DATA
The SCISETINT register is used to enable the various interrupts available in the LIN module.
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| Instance Name | Physical Address |
|---|---|
| LIN0 | 5240 000Ch |
| LIN1 | 5240 100Ch |
| LIN2 | 5240 200Ch |
| LIN3 | 5240 300Ch |
| LIN4 | 5240 400Ch |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| SETBEINT | SETPBEINT | SETCEINT | SETISFEINT | SETNREINT | SETFEINT | SETOEINT | SETPEINT |
| R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS |
| 0h | 0h | 0h | 0h | 0h | 0h | 0h | 0h |
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED_5 | SET_RX_DMA_ALL | SET_RX_DMA | SET_TX_DMA | ||||
| R | R/W1TS | R/W1TS | R/W1TS | ||||
| 0h | 0h | 0h | 0h | ||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED_4 | SETIDINT | RESERVED_3 | SETRXINT | SETTXINT | |||
| R | R/W1TS | R | R/W1TS | R/W1TS | |||
| 0h | 0h | 0h | 0h | 0h | |||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| SETTOA3WUSINT | SETTOAWUSINT | RESERVED_2 | SETTIMEOUTINT | RESERVED_1 | SETWAKEUPINT | SETBRKDTINT | |
| R/W1TS | R/W1TS | R | R/W1TS | R | R/W1TS | R/W1TS | |
| 0h | 0h | 0h | 0h | 0h | 0h | 0h | |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31 | SETBEINT | R/W1TS | 0h | Set bit error interrupt. This bit is effective in LIN mode only. Setting this bit enables the SCI/LIN module to generate an interrupt when there is a bit error. This field is writable in LIN mode only. 1 Interrupt is enabled.
0 Interrupt is disabled. Writing a 0 to this
bit has no effect. |
| 30 | SETPBEINT | R/W1TS | 0h | Set physical bus error interrupt. This bit is effective in LIN mode only. Setting this bit enables the SCI/LIN module to generate an interrupt when a physical bus error occurs. This field is writable in LIN mode only. 1 Interrupt is enabled.
0 Interrupt is disabled. Writing a 0 to this
bit has no effect. |
| 29 | SETCEINT | R/W1TS | 0h | Set checksum-error Interrupt. This bit is effective in LIN mode only. Setting this bit enables the SCI/LIN module to generate an interrupt when there is a checksum error. This field is writable in LIN mode only. 1 Interrupt is enabled.
0 Interrupt is disabled. Writing a 0 to this
bit has no effect. |
| 28 | SETISFEINT | R/W1TS | 0h | Set inconsistent-sync-field-error interrupt. This bit is effective in LIN mode only. Setting this bit enables the SCI/LIN module to generate an interrupt when there is an inconsistent sync field error. This field is writable in LIN mode only. 1 Interrupt is enabled.
0 Interrupt is disabled. Writing a 0 to this
bit has no effect. |
| 27 | SETNREINT | R/W1TS | 0h | Set no-response-error interrupt. This bit is effective in LIN mode only. Setting this bit enables the SCI/LIN module to generate an interrupt when a no-response error occurs. This field is writable in LIN mode only. 1 Interrupt is enabled.
0 Interrupt is disabled. Writing a 0 to this
bit has no effect. |
| 26 | SETFEINT | R/W1TS | 0h | Set framing-error interrupt. This bit is effective in LIN or SCI-compatible mode. Setting this bit enables the SCI/LIN module to generate an interrupt when a framing error occurs. 1 Interrupt is enabled.
0 Interrupt is disabled. Writing a 0 to this
bit has no effect. |
| 25 | SETOEINT | R/W1TS | 0h | Set overrun-error interrupt. This bit is effective in LIN or SCI-compatible mode. Setting this bit enables the SCI/LIN module to generate an interrupt when an overrun error occurs. 1 Interrupt is enabled.
0 Interrupt is disabled. Writing a 0 to this
bit has no effect. |
| 24 | SETPEINT | R/W1TS | 0h | Set parity interrupt. This bit is effective in LIN or SCI-compatible mode. Setting this bit enables the SCI/LIN module to generate an interrupt when a parity error occurs. 1 Interrupt is enabled.
0 Interrupt is disabled. Writing a 0 to this
bit has no effect. |
| 23:19 | RESERVED_5 | R | 0h | Reserved |
| 18 | SET_RX_DMA_ALL | R/W1TS | 0h | Set receiver DMA for Address & Data frames. This bit is effective in LIN or SCI-compatible mode. To enable RX DMA request for address and data frames this bit must be set. If it is cleared, RX interrupt request is generated for address frames and DMA requests are generated for data frames. 1 Receiver DMA request is enabled for address
and data frames
0 Receiver DMA request is disabled for
address frames (RX interrupt request is
enabled for address frames). Writing a 0 to
this bit has no effect. |
| 17 | SET_RX_DMA | R/W1TS | 0h | Set receiver DMA. This bit is effective in LIN or SCI-compatible mode. To enable DMA requests for the receiver this bit must be set. If it is cleared, interrupt requests are generated depending on SETRXINT. 1 Receiver DMA request is enabled.
0 Receiver DMA request is disabled. Writing a
0 to this bit has no effect. |
| 16 | SET_TX_DMA | R/W1TS | 0h | Set transmit DMA. This bit is effective in LIN or SCI-compatible mode. To enable DMA requests for the transmitter, this bit must be set. If it is cleared, interrupt requests are generated depending on SETTXINT. 1 Transmit DMA request is enabled
0 Transmit DMA request is disabled. Writing a
0 to this bit has no effect. |
| 15:14 | RESERVED_4 | R | 0h | Reserved |
| 13 | SETIDINT | R/W1TS | 0h | Set Identification interrupt. This bit is effective in LIN mode only. This bit is set to enable interrupt once a valid matching identifier is received. 1 Interrupt is enabled.
0 Interrupt is disabled. Writing a 0 to this
bit has no effect. |
| 12:10 | RESERVED_3 | R | 0h | Reserved |
| 9 | SETRXINT | R/W1TS | 0h | Set Receiver interrupt. Setting this bit enables the SCI/LIN to generate a receive interrupt after a frame has been completely received and the data is being transferred from SCIRXSHF to SCIRD. 1 Interrupt is enabled.
0 Interrupt is disabled. Writing a 0 to this
bit has no effect. |
| 8 | SETTXINT | R/W1TS | 0h | Set Transmitter interrupt. Setting this bit enables the SCI/LIN to generate a transmit interrupt as data is being transferred from SCITD to SCITXSHF and the TXRDY bit is being set. 1 Interrupt is enabled.
0 Interrupt is disabled. Writing a 0 to this
bit has no effect. |
| 7 | SETTOA3WUSINT | R/W1TS | 0h | Set Timeout After 3 Wakeup Signals interrupt. This bit is effective in LIN mode only. Setting this bit enables the SCI/LIN to generate an interrupt when there is a timeout after 3 wakeup signals have been sent. This field is writable in LIN mode only. 1 Interrupt is enabled.
0 Interrupt is disabled. Writing a 0 to this
bit has no effect. |
| 6 | SETTOAWUSINT | R/W1TS | 0h | Set Timeout After Wakeup Signal interrupt. This bit is effective in LIN mode only. Setting this bit enables the SCI/LIN to generate an interrupt when there is a timeout after one wakeup signal has been sent. This field is writable in LIN mode only. 1 Interrupt is enabled.
0 Interrupt is disabled. Writing a 0 to this
bit has no effect. |
| 5 | RESERVED_2 | R | 0h | Reserved |
| 4 | SETTIMEOUTINT | R/W1TS | 0h | Set timeout interrupt. This bit is effective in LIN mode only. Setting this bit enables the SCI/LIN to generate an interrupt when no LIN bus activity [bus idle] occurs for at least 4 seconds. This field is writable in LIN mode only. 1 Interrupt is enabled.
0 Interrupt is disabled. Writing a 0 to this
bit has no effect. |
| 3:2 | RESERVED_1 | R | 0h | Reserved |
| 1 | SETWAKEUPINT | R/W1TS | 0h | Set wake-up interrupt. This bit is effective in LIN or SCI-compatible mode. Setting this bit enables the SCI/LIN to generate a wake-up interrupt and thereby exit low-power mode. The wake-up interrupt is asserted on falling edge of the wake-up pulse. If enabled, the wake-up interrupt is asserted when local low-power mode is requested while the receiver is busy or if a low level is detected on the SCIRX pin during low-power mode. Wake-up interrupt is not asserted upon a wakeup pulse if the module is not in power down mode. 1 Interrupt is enabled.
0 Interrupt is disabled. Writing a 0 to this
bit has no effect. |
| 0 | SETBRKDTINT | R/W1TS | 0h | Set break-detect interrupt. This bit is effective in SCI-compatible mode only. Setting this bit enables the SCI/LIN to generate an interrupt if a break condition is detected on the LINRX pin. This field is writable in SCI mode only. 1 Interrupt is enabled.
0 Interrupt is disabled. Writing a 0 to this
bit has no effect. |