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SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1

PRODUCTION DATA

5.11.2.3 LIN_SCIGCR2 Register

11.2.3.1 LIN_SCIGCR2 Register (Offset = 8h) [reset = 0h]

The SCIGCR2 register is used to send or compare a checksum byte during extended frames, to generate a wakeup and for low-power mode control of the LIN module.

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Table 5-1296 Instance Table

Instance Name	Physical Address
LIN0	5240 0008h
LIN1	5240 1008h
LIN2	5240 2008h
LIN3	5240 3008h
LIN4	5240 4008h

Figure 5-641 LIN_SCIGCR2 Name Register

31	30	29	28	27	26	25	24
RESERVED_3
R
0h
23	22	21	20	19	18	17	16
RESERVED_3						CC	SC
R						R/W	R/W
0h						0h	0h
15	14	13	12	11	10	9	8
RESERVED_2							GENWU
R							R/W
0h							0h
7	6	5	4	3	2	1	0
RESERVED_1							POWERDOWN
R							R/W
0h							0h

Table 5-1297 LIN_SCIGCR2 Register Field Descriptions

Bit	Field	Type	Reset	Description
31:18	RESERVED_3	R	0h	Reserved
17	CC	R/W	0h	Compare Checksum. This mode is effective in LIN mode only. This bit is used by the receiver for extended frames to trigger a checksum compare. The user will initiate this transaction by Writing a one to this bit. In non multibuffer mode, once the CC bit is set, the checksum will be compared on the byte that is currently being received, expected to be the checkbyte. During Multi-buffer mode, following are the scenarios associated with the CC bit : - If CC bit is set during the reception of the data, then the byte that is received after the reception of the programmed no. of data bytes indicated by SCIFORMAT[18:16], is treated as a checksum byte. - If CC bit is set during the IDLE period [i.e. during inter-frame space], then the next immediate byte will be treated as a checksum byte. A CE will immediatly be flagged if there is a checksum error. This bit is automatically cleared once the checksum is successfully compared. 1 Compare checksum on expected checkbyte 0 No effect
16	SC	R/W	0h	Send Checksum This mode is effective in LIN mode only. This bit is used by the transmitter with extended frames to send a checkbyte. In non multibuffer mode the checkbyte will be sent after the current byte transmission. In multibuffer mode the checkbyte will be sent after the last byte count, indicated by the SCIFORMAT[18:16]]. This field is writable in LIN mode only. 1 A checkbyte will be sent. This bit will automatically get cleared after the checkbyte is transmitted. The checksum will not be sent if this bit is set before transmitting the very first byte, that is, during interframe space. 0 No checkbyte will be sent.
15:9	RESERVED_2	R	0h	Reserved
8	GENWU	R/W	0h	Generate wakeup signal. This bit controls the generation of a wakeup signal, by transmitting the TDO buffer value. This bit is cleared on reception of a valid sync break. 1 Transmit TDO for wakeup. This bit will be cleared on a SWnRST (SCIGCR1.7) 0 No effect
7:1	RESERVED_1	R	0h	Reserved
0	POWERDOWN	R/W	0h	Power down. This bit is effective in LIN or SCI-compatible mode. When the powerdown bit is set, the SCI/LIN module attempts to enter local low-power mode. If the POWERDOWN bit is set while the receiver is actively receiving data and the wakeup interrupt is disabled, then the SCI/LIN will delay low-power mode from being entered until completion of reception. In LIN mode the user may set the POWERDOWN bit on Sleep Command reception or on idle bus detection [more than 4 seconds, i.e. 80,000 cycles at 20kHz] 1 Request local low-power mode 0 Normal operation