SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1
PRODUCTION DATA
The SCIGCR1 register defines the frame format, protocol, and communication mode used by the SCI.
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| Instance Name | Physical Address |
|---|---|
| LIN0 | 5240 0004h |
| LIN1 | 5240 1004h |
| LIN2 | 5240 2004h |
| LIN3 | 5240 3004h |
| LIN4 | 5240 4004h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED_3 | TXENA | RXENA | |||||
| R | R/W | R/W | |||||
| 0h | 0h | 0h | |||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED_2 | CONT | LOOPBACK | |||||
| R | R/W | R/W | |||||
| 0h | 0h | 0h | |||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED_1 | STOPEXTFRAME | HGENCTRL | CTYPE | MBUFMODE | ADAPT | SLEEP | |
| R | R/W | R/W | R/W | R/W | R/W | R/W | |
| 0h | 0h | 0h | 0h | 0h | 0h | 0h | |
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| SWNRST | LINMODE | CLK_MASTER | STOP | PARITY | PARITYENA | TIMINGMODE | COMMMODE |
| R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W |
| 0h | 0h | 0h | 0h | 0h | 0h | 0h | 0h |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:26 | RESERVED_3 | R | 0h | Reserved |
| 25 | TXENA | R/W | 0h | Transmit enable. This bit is effective in LIN and SCI modes. Data is transferred from SCITD or the TDy [with y=0, 1,...7] buffers in LIN mode to the SCITXSHF shift out register only when the TXENA bit is set. Note: Data written to SCITD or the transmit multi-buffer before TXENA is set is not transmitted. If TXENA is cleared while transmission is ongoing, the data previously written to SCITD is sent [including the checksum byte in LIN mode]. 1 Enable transfers of data from SCITD or TDy
to SCITXSHF
0 Disable transfers from SCITD or TDy to
SCITXSHF |
| 24 | RXENA | R/W | 0h | Receive enable. This bit is effective in LIN or SCI-compatible mode. RXENA allows or prevents the transfer of data from SCIRXSHF to SCIRD or the receive multibuffers. Note: Clearing RXENA stops received characters from being transferred into the receive buffer or multi-buffers, prevents the RX status flags [see Table 7] from being updated by receive data, and inhibits both receive and error interrupts. However, the shift register continues to assemble data regardless of the state of RXENA. Note: If RXENA is cleared before the time the reception of a frame is complete, the data from the frame is not transferred into the receive buffer. Note: If RXENA is set before the time the reception of a frame is complete, the data from the frame is transferred into the receive buffer. If RXENA is set while SCIRXSHF is in the process of assembling a frame, the status flags are not guaranteed to be accurate for that frame. To ensure that the status flags correctly reflect what was detected on the bus during a particular frame, RXENA should be set before the detection of that frame 1 Allows the receiver to transfer data from
the shift buffer to the receive buffer or
multi-buffers
0 Prevents the receiver from transferring
data from the shift buffer to the receive
buffer or multi-buffers |
| 23:18 | RESERVED_2 | R | 0h | Reserved |
| 17 | CONT | R/W | 0h | Continue on suspend. This bit has an effect only when a program is being debugged with an emulator, and it determines how the SCI/LIN operates when the program is suspended. This bit affects the LIN counters. When this bit is set, the counters are not stopped during debug. When this bit is cleared, the counters are stopped during debug. 1 When debug mode is entered, the SCI/LIN
continues to operate until the current
transmit and receive functions are
complete.
0 When debug mode is entered, the SCI/LIN
state machine is frozen. Transmissions and
LIN counters are halted and resume when
debug mode is exited. |
| 16 | LOOPBACK | R/W | 0h | Loopback bit. This bit is effective in LIN or SCI-compatible mode. The self-checking option for the SCI/LIN can be selected with this bit. If the LINTX and LINRX pins are configured with SCI/LIN functionality, then the LINTX pin is internally connected to the LINRX pin. Externally, during loop back operation, the LINTX pin outputs a high value and the LINRX pin is in a high-impedance state. If this bit value is changed while the SCI/LIN is transmitting or receiving data, errors may result. 1 Loopback mode is enabled. 0 Loopback mode is disabled. |
| 15:14 | RESERVED_1 | R | 0h | Reserved |
| 13 | STOPEXTFRAME | R/W | 0h | Stop extended frame communication. This bit is effective in LIN mode only. This bit can be written only during extended frame communication. When the extended frame communication is stopped, this bit is cleared automatically. 1 Extended frame communication will be
stopped, once current frame
transmission/reception is completed.
0 No effect |
| 12 | HGENCTRL | R/W | 0h | HGEN control bit. This bit is effective in LIN mode only. This bit controls the type of mask filtering comparison. 1 ID filtering using ID-SlaveTask byte
(Recommended). |
| 11 | CTYPE | R/W | 0h | Checksum type. This bit is effective in LIN mode only. This bit controls the type of checksum to be used: classic or enhanced. 1 Enhanced checksum is used. |
| 10 | MBUFMODE | R/W | 0h | Multibuffer mode. This bit is effective in LIN or SCI-compatible mode. This bit controls receive/transmit buffer usage, that is, whether the RX/TX multibuffers are used or a single register, RD0/TD0, is used. 1 The multi-buffer mode is enabled. 0 The multi-buffer mode is disabled. |
| 9 | ADAPT | R/W | 0h | Adapt mode enable. This mode is effective in LIN mode only. This bit has an effect during the detection of the Sync Field. There are two LIN protocol bit rate modes that could be enabled with this bit according to the Node capability file definition: automatic or select. Software and network configuration will decide which of the previous two modes. When this bit is cleared, the LIN 2.0 protocol fixed bit rate should be used. If the ADAPT bit is set, a LIN target node detecting the baudrate will compare it to the prescalers in BRSR register and update it if they are different. The BRSR register will be updated with the new value. If this bit is not set there will be no adjustment to the BRSR register. This field is writable in LIN mode only. 1 Automatic baudrate adjustment is enabled. 0 Automatic baudrate adjustment is disabled. |
| 8 | SLEEP | R/W | 0h | SCI sleep. SCI compatibility mode only. In a multiprocessor configuration, this bit controls the receive sleep function. Clearing this bit brings the SCI out of sleep mode. The receiver still operates when the SLEEP bit is set; however, RXRDY is updated and SCIRD is loaded with new data only when an address frame is detected. The remaining receiver status flags are updated and an error interrupt is requested if the corresponding interrupt enable bit is set, regardless of the value of the SLEEP bit. In this way, if an error is detected on the receive data line while the SCI is asleep, software can promptly deal with the error condition. The SLEEP bit is not automatically cleared when an address byte is detected. This field is writable in SCI mode only. 1 Sleep mode is enabled. 0 Sleep mode is disabled. |
| 7 | SWNRST | R/W | 0h | Software reset [active low]. This bit is effective in LIN or SCI-compatible mode. The SCI/LIN should only be configured while SWnRST = 0. Only the following configuration bits can be changed in runtime [i.e., while SWnRESET = 1]: - STOP EXT Frame [SCIGCR1[13]] - CC bit [SCIGCR2[17]] - SC bit [SCIGCR2[16]] 1 The SCI/LIN is in its ready state;
transmission and reception can occur. After
this bit is set to 1, the configuration of
the module should not change.
0 The SCI/LIN is in its reset state; no data
will be transmitted or received. Writing a
0 to this bit intializes the SCI/LIN state
machines and operating flags. All affected
logic is held in the reset state until a 1
is written to this bit. |
| 6 | LINMODE | R/W | 0h | LIN mode This bit controls the mode of operation of the module. 1 LIN mode is enabled; SCI compatibility mode
is disabled.
0 LIN mode is disabled; SCI compatibility
mode is enabled. |
| 5 | CLK_MASTER | R/W | 0h | SCI internal clock enable or LIN Master/Target configuration. In the SCI mode, this bit enables the clock to the SCI module. In LIN mode, this bit determines whether a LIN node is a target or master. 1 SCI-compatible mode: Enable clock to the
SCI module. |
| 4 | STOP | R/W | 0h | SCI number of stop bits. This bit is effective in SCI-compatible mode only. Note: The receiver checks for only one stop bit. However in idle-line mode, the receiver waits until the end of the second stop bit [if STOP = 1] to begin checking for an idle period. This field is writable in SCI mode only. 1 Two stop bits are used. 0 One stop bit is used. |
| 3 | PARITY | R/W | 0h | SCI parity odd/even selection. This bit is effective in SCI-compatible mode only. If the PARITY ENA bit [SCIGCR1.2] is set, PARITY designates odd or even parity. The parity bit is calculated based on the data bits in each frame and the address bit [in address-bit mode]. The start and stop fields in the frame are not included in the parity calculation. This field is writable in SCI mode only. 1 Even parity is used. The SCI transmits and
expects to receive a value in the parity
bit that makes even the total number of
bits in the frame with the value of 1.
0 Odd parity is used. The SCI transmits and
expects to receive a value in the parity
bit that makes odd the total number of bits
in the frame with the value of 1. |
| 2 | PARITYENA | R/W | 0h | Parity enable. Enables or disables the parity function. 1 SCI compatible mode: Parity enabled. A
parity bit is generated during transmission
and is expected during reception. |
| 1 | TIMINGMODE | R/W | 0h | SCI timing mode bit. This bit is effective in SCI-compatible mode only. It must be set to 1 when the SCI mode is used. This bit configures the SCI for asynchronous operation. 1 Must be set to 1 when module is configured
for SCI operation
0 Reserved. |
| 0 | COMMMODE | R/W | 0h | SCI/LIN communication mode bit. In compatibility mode, it selects the SCI communication mode. In LIN mode it selects length control option for ID-field bits ID4 and ID5. 1 SCI-compatible mode: Address-bit mode is
used. |