SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1
PRODUCTION DATA
I2C Extended Mode register
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| Instance Name | Physical Address |
|---|---|
| I2C0 | 5250 002Ch |
| I2C1 | 5250 102Ch |
| I2C2 | 5250 202Ch |
| I2C3 | 5250 302Ch |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| NU | |||||||
| R/W | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| NU | |||||||
| R/W | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| NU | |||||||
| R/W | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| NU | IGNACK | BCM | |||||
| R/W | R/W | R/W | |||||
| 0h | 0h | 0h | |||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:2 | NU | R/W | 0h | Reserved. - [RW ] |
| 1 | IGNACK | R/W | 0h | Ignore NACK mode IGNACK=0 The master transmitter will operate normally discontinue the data transfer and set the ARDY and NACK status bits when a NACK signal is received from the target. IGNACK=1 The master transmitter will ignore a NACK received from the target. |
| 0 | BCM | R/W | 0h | Backward Compatibility Mode. This bit affects the I2C interrupt behavior. Refer to appendix A for details. |