SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1
PRODUCTION DATA
I2C Clock Divider Low register
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| Instance Name | Physical Address |
|---|---|
| I2C0 | 5250 000Ch |
| I2C1 | 5250 100Ch |
| I2C2 | 5250 200Ch |
| I2C3 | 5250 300Ch |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| NU | |||||||
| R/W | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| NU | |||||||
| R/W | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| ICCL15_ICCL0 | |||||||
| R/W | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| ICCL15_ICCL0 | |||||||
| R/W | |||||||
| 0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:16 | NU | R/W | 0h | Reserved |
| 15:0 | ICCL15_ICCL0 | R/W | 0h | Low time I 2 C SCL Clock Division Factor. They are used to divide down the master clock to create the SCL low time transition frequency. This register must be configured while the I2C is still in reset [IRS_=0]. |