SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1
PRODUCTION DATA
Transmit user-defined CRC register.
Return to Summary Table
| Instance Name | Physical Address |
|---|---|
| FSI_TX0 | 5028 0030h |
| FSI_TX1 | 5028 1030h |
| FSI_TX2 | 502A 0030h |
| FSI_TX3 | 502A 1030h |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED_1 | |||||||
| R | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| USER_CRC | |||||||
| R/W | |||||||
| 0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15:8 | RESERVED_1 | R | 0h | Reserved |
| 7:0 | USER_CRC | R/W | 0h | User-defined CRC This register contains the 8-bit CRC value to be transmitted in the next frame if the transmission is set for user-defined CRC option [TX_OPER_CTRL_LO.SW_CRC = 1]. This register is ignored if the hardware CRC generation is enabled. |