SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1
PRODUCTION DATA
QDMA Event Missed Register: The QDMA Event Missed register is set if 2 QDMA events are detected without the first event being cleared or if a Null TR is serviced.. If any bit in the QEMR register is set (and all errors (including EMR/CCERR) were previously clear) then an error will be signaled with TPCC error interrupt.
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| Instance Name | Physical Address |
|---|---|
| EDMA0 | 52A0 0310h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RES31 | |||||||
| R | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RES31 | |||||||
| R | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RES31 | |||||||
| R | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| E7 | E6 | E5 | E4 | E3 | E2 | E1 | E0 |
| R | R | R | R | R | R | R | R |
| 0h | 0h | 0h | 0h | 0h | 0h | 0h | 0h |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:8 | RES31 | R | 0h | RESERVE FIELD |
| 7 | E7 | R | 0h | Event Missed #7 |
| 6 | E6 | R | 0h | Event Missed #6 |
| 5 | E5 | R | 0h | Event Missed #5 |
| 4 | E4 | R | 0h | Event Missed #4 |
| 3 | E3 | R | 0h | Event Missed #3 |
| 2 | E2 | R | 0h | Event Missed #2 |
| 1 | E1 | R | 0h | Event Missed #1 |
| 0 | E0 | R | 0h | Event Missed #0 |