SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1
PRODUCTION DATA
Interrupt Register. The flags are set when one of the listed conditions is detected (edge-sensitive). The flags remain set until the Host CPU clears them. A flag is cleared by writing a 1h to the corresponding bit position. Writing a 0h has no effect.
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| Instance Name | Physical Address |
|---|---|
| MCAN0 | 5260 8250h |
| MCAN1 | 5261 8250h |
| MCAN2 | 5262 8250h |
| MCAN3 | 5263 8250h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| NU30 | ARA | PED | PEA | WDI | BO | EW | |
| R | R/W | R/W | R/W | R/W | R/W | R/W | |
| 0h | 0h | 0h | 0h | 0h | 0h | 0h | |
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| EP | ELO | BEU | BEC | DRX | TOO | MRAF | TSW |
| R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W |
| 0h | 0h | 0h | 0h | 0h | 0h | 0h | 0h |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| TEFL | TEFF | TEFW | TEFN | TFE | TCF | TC | HPM |
| R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W |
| 0h | 0h | 0h | 0h | 0h | 0h | 0h | 0h |
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RF1L | RF1F | RF1W | RF1N | RF0L | RF0F | RF0W | RF0N |
| R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W |
| 0h | 0h | 0h | 0h | 0h | 0h | 0h | 0h |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:30 | NU30 | R | 0h | Reserved |
| 29 | ARA | R/W | 0h | Access to Reserved Address |
| 28 | PED | R/W | 0h | Protocol Error in data Phase |
| 27 | PEA | R/W | 0h | Protocol Error in Arbitration Phase |
| 26 | WDI | R/W | 0h | Watchdog Interrupt |
| 25 | BO | R/W | 0h | Bus_Off Status |
| 24 | EW | R/W | 0h | Warning Status |
| 23 | EP | R/W | 0h | Error Passive |
| 22 | ELO | R/W | 0h | Error Logging Overflow |
| 21 | BEU | R/W | 0h | Bit Error Uncorrected |
| 20 | BEC | R/W | 0h | Bit Error Corrected |
| 19 | DRX | R/W | 0h | Message stored to Dedicated Rx Buffer |
| 18 | TOO | R/W | 0h | Timeout Occurred |
| 17 | MRAF | R/W | 0h | Message RAM Access Failure The flag is set, when the Rx Handler: i. has not completed acceptance filtering or storage of an accepted message until the arbitration field of the following message has been received. In this case acceptance filtering or message storage is aborted and the Rx Handler starts processing of the following message. ii. was not able to write a message to the Message RAM. In this case message storage is aborted. In both cases the FIFO put index is not updated respectively the New Data flag for a dedicated Rx Buffer is not set, a partly stored message is overwritten when the next message is stored to this location. The flag is also set when the Tx Handler was not able to read a message from the Message RAM in time. In this case message transmission is aborted. In case of a Tx Handler access failure the MCAN module is switched into Restricted Operation Mode (see Restricted Operation Mode). To leave Restricted Operation Mode, the Host CPU has to reset the MCAN_CCCR[2] ASM bit. 1'b0 = No Message RAM access failure occurred 1'b1 = Message RAM access failure occurred |
| 16 | TSW | R/W | 0h | Timestamp Wraparound |
| 15 | TEFL | R/W | 0h | Tx Event FIFO Element Lost |
| 14 | TEFF | R/W | 0h | Tx Event FIFO Full |
| 13 | TEFW | R/W | 0h | Tx Event FIFO Watermark Reached |
| 12 | TEFN | R/W | 0h | Tx Event FIFO New Entry |
| 11 | TFE | R/W | 0h | Tx FIFO Empty |
| 10 | TCF | R/W | 0h | Transmission Cancellation Finished |
| 9 | TC | R/W | 0h | Transmission Complete |
| 8 | HPM | R/W | 0h | High Priority Message |
| 7 | RF1L | R/W | 0h | Rx FIFO 1 Message Lost |
| 6 | RF1F | R/W | 0h | Rx FIFO 1 Full |
| 5 | RF1W | R/W | 0h | Rx FIFO 1 Watermark Reached |
| 4 | RF1N | R/W | 0h | Rx FIFO 1 New Message |
| 3 | RF0L | R/W | 0h | Rx FIFO 0 Message Lost |
| 2 | RF0F | R/W | 0h | Rx FIFO 0 Full |
| 1 | RF0W | R/W | 0h | Rx FIFO 0 Watermark Reached |
| 0 | RF0N | R/W | 0h | Rx FIFO 0 New Message |