SPRUJ42 User guide | 德州仪器 TI.com.cn

SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1

PRODUCTION DATA

5.2.23.1 MSS_TOPRCM_PLL_CORE_HSDIVIDER Register (Offset = 428h) [reset = 0h]

Core PLL high speed divider config.

Table 2-1452 Instance Table

Instance Name	Physical Address
MSS_TOPRCM	5320 0428h

Figure 2-724 MSS_TOPRCM_PLL_CORE_HSDIVIDER Name Register

31	30	29	28	27	26	25	24
RESERVED
NONE
0h
23	22	21	20	19	18	17	16
RESERVED						PLL_CORE_HSDIVIDER_LDOPWDNACK	PLL_CORE_HSDIVIDER_BYPASSACKZ
NONE						R	R
0h						0h	0h
15	14	13	12	11	10	9	8
RESERVED
NONE
0h
7	6	5	4	3	2	1	0
RESERVED					PLL_CORE_HSDIVIDER_TENABLEDIV	PLL_CORE_HSDIVIDER_LDOPWDN	PLL_CORE_HSDIVIDER_BYPASS
NONE					R/W	R/W	R/W
0h					0h	0h	0h

Table 2-1453 MSS_TOPRCM_PLL_CORE_HSDIVIDER Register Field Descriptions

Bit	Field	Type	Reset	Description
31:18	RESERVED	NONE	0h	Reserved
17	PLL_CORE_HSDIVIDER_LDOPWDNACK	R	0h	LDO Power Down Ack
16	PLL_CORE_HSDIVIDER_BYPASSACKZ	R	0h	HSDIVIDER Bypass Ack
15:3	RESERVED	NONE	0h	Reserved
2	PLL_CORE_HSDIVIDER_TENABLEDIV	R/W	0h	TENABLEDIV rising edge loads the values of M2REG and N2REG into ADPLLLJ register. TENABLEDIV could be activated anytime when the DPLL digital is in power-up condition. M2 and N2 latch [active rise edge]
1	PLL_CORE_HSDIVIDER_LDOPWDN	R/W	0h	1'b1 indicates ADPLLLJ internal LDO is power down. VDDLDOOUT will be un-defined in this condition
0	PLL_CORE_HSDIVIDER_BYPASS	R/W	0h	HSDIVIDER Bypass. Set it to 1'b1 to bypass the HSDIVIDER.