SPRUJ42 User guide | 德州仪器 TI.com.cn

SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1

PRODUCTION DATA

2.5.2.22 MSS_TOPRCM_PLL_CORE_STATUS Register

5.2.22.1 MSS_TOPRCM_PLL_CORE_STATUS Register (Offset = 424h) [reset = E0001141h]

Core PLL status regiser.

Table 2-1450 Instance Table

Instance Name	Physical Address
MSS_TOPRCM	5320 0424h

Figure 2-723 MSS_TOPRCM_PLL_CORE_STATUS Name Register

31	30	29	28	27	26	25	24
PLL_CORE_STATUS_PONOUT	PLL_CORE_STATUS_PGOODOUT	PLL_CORE_STATUS_LDOPWDN	PLL_CORE_STATUS_RECAL_BSTATUS3	PLL_CORE_STATUS_RECAL_OPPIN	RESERVED
R	R	R	R	R	NONE
1h	1h	1h	0h	0h	0h
23	22	21	20	19	18	17	16
RESERVED
NONE
0h
15	14	13	12	11	10	9	8
RESERVED			PLL_CORE_STATUS_CLKOUTLDOENACK	PLL_CORE_STATUS_CLKDCOLDOACK	PLL_CORE_STATUS_PHASELOCK	PLL_CORE_STATUS_FREQLOCK	PLL_CORE_STATUS_BYPASSACK
NONE			R	R	R	R	R
0h			1h	0h	0h	0h	1h
7	6	5	4	3	2	1	0
PLL_CORE_STATUS_STBYRETACK	PLL_CORE_STATUS_LOSSREF	PLL_CORE_STATUS_CLKOUTENACK	PLL_CORE_STATUS_LOCK2	PLL_CORE_STATUS_M2CHANGEACK	PLL_CORE_STATUS_SSCACK	PLL_CORE_STATUS_HIGHJITTER	PLL_CORE_STATUS_BYPASS
R	R	R	R	R	R	R	R
0h	1h	0h	0h	0h	0h	0h	1h

Table 2-1451 MSS_TOPRCM_PLL_CORE_STATUS Register Field Descriptions

Bit	Field	Type	Reset	Description
31	PLL_CORE_STATUS_PONOUT	R	1h	Status of the weak power-switch 0x0 : indicates the/OFF status of the weak power-switch in digital to SOC. 0x1 : ndicates the ON status of the weak power-switch in digital to SOC.
30	PLL_CORE_STATUS_PGOODOUT	R	1h	Status of the strong power-switch 0x0 : indicates the/OFF status of the strong power-switch in digital to SOC. 0x1 : ndicates the ON status of the strong power-switch in digital to SOC.
29	PLL_CORE_STATUS_LDOPWDN	R	1h	1'b1 indicates ADPLLLJ internal LDO is power down. VDDLDOOUT will be un-defined in this condition
28	PLL_CORE_STATUS_RECAL_BSTATUS3	R	0h	Recalibration status flag. 1'b1 ADPLLLJ requires recalibration
27	PLL_CORE_STATUS_RECAL_OPPIN	R	0h	Recalibration status flag. 1'b1 ADPLLLJ requires recalibration
26:13	RESERVED	NONE	0h	Reserved
12	PLL_CORE_STATUS_CLKOUTLDOENACK	R	1h	Indicates the enable/disable condition of CLKOUTLDOEN 0x0 = CLKOUTLDO gating completed 0x1 = CLKOUTLDO enabling completed
11	PLL_CORE_STATUS_CLKDCOLDOACK	R	0h	Indicates the enable/disable condition of CLKDCOLDOEN 0x0 = CLKDCOLDO gating completed 0x1 = CLKDCOLOD enabling completed
10	PLL_CORE_STATUS_PHASELOCK	R	0h	Status on PHASELOCK output pin
9	PLL_CORE_STATUS_FREQLOCK	R	0h	Status on FREQLOCK output pin
8	PLL_CORE_STATUS_BYPASSACK	R	1h	Status of BYPASSACK output pin
7	PLL_CORE_STATUS_STBYRETACK	R	0h	Standby and retention status 0x0: indicates to SOC that all internal clocks in ADPLLLJ are active and it is starting the relock process. 0x1: indicates to SOC that all internal clocks in ADPLLLJ are gated and it is ready for retention.
6	PLL_CORE_STATUS_LOSSREF	R	1h	Reference input loss is indicated by 1'b0.
5	PLL_CORE_STATUS_CLKOUTENACK	R	0h	Indicates the enable/disable condition of CLKOUTEN 0x0 = CLKOUT gating completed 0x1 = CLKOUT enabling completed
4	PLL_CORE_STATUS_LOCK2	R	0h	ADPLL internal loop lock status
3	PLL_CORE_STATUS_M2CHANGEACK	R	0h	Acknowledge for change to M2 divider. Toggles from 1-0 or 0-1 [depending on current value] once CLKOUT frequency change has completed.
2	PLL_CORE_STATUS_SSCACK	R	0h	Spread Spectrum status 0x0 : Spread-spectrum Clocking is disabled on output clocks 0x1 : Spread-spectrum Clocking is enabled on output clocks
1	PLL_CORE_STATUS_HIGHJITTER	R	0h	1'b1 indicates jitter. After PHASELOCK is asserted high, the HIGHJITTER flag is asserted high if phase error between REFCLK and FBCLK greater than 24%.
0	PLL_CORE_STATUS_BYPASS	R	1h	Bypass status signal. 1 CLKOUT in bypass