SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1
PRODUCTION DATA
ECC Error Status1 Register.
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| Instance Name | Physical Address |
|---|---|
| ECC_AGGR | 5301 0020h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| ECC_BIT1 | |||||||
| R | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| ECC_BIT1 | |||||||
| R | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| CLR_CTRL_REG_ERR | CLR_PARITY_ERR | CLR_ECC_OTHER | CLR_ECC_DED | CLR_ECC_SEC | |||
| R/W1TC | R/WD | R/W1TC | R/WD | R/WD | |||
| 0h | 0h | 0h | 0h | 0h | |||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| CTR_REG_ERR | PARITY_ERR | ECC_OTHER | ECC_DED | ECC_SEC | |||
| R/W1TS | R/W1TS | R/W1TS | R/WI | R/WI | |||
| 0h | 0h | 0h | 0h | 0h | |||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:16 | ECC_BIT1 | R | 0h | Data bit that corresponds to the single-bit error |
| 15 | CLR_CTRL_REG_ERR | R/W1TC | 0h | Clear control reg error Error Status, you must also re write the contorl ergister itself to clear this |
| 14:13 | CLR_PARITY_ERR | R/WD | 0h | Clear parity Error Status |
| 12 | CLR_ECC_OTHER | R/W1TC | 0h | Clear other Error Status |
| 11:10 | CLR_ECC_DED | R/WD | 0h | Clear Double Bit Error Status |
| 9:8 | CLR_ECC_SEC | R/WD | 0h | Clear Single Bit Error Status |
| 7 | CTR_REG_ERR | R/W1TS | 0h | control register error pending, Level interrupt |
| 6:5 | PARITY_ERR | R/W1TS | 0h | Level parity error Error Status |
| 4 | ECC_OTHER | R/W1TS | 0h | Successive single-bit errors have occurred while a writeback is still pending, Level interrupt |
| 3:2 | ECC_DED | R/WI | 0h | Level Double Bit Error Status |
| 1:0 | ECC_SEC | R/WI | 0h | Level Single Bit Error Status |