Sitara 处理器:四核 Arm Cortex-A53 和双核 Arm Cortex-R5F,千兆位 PRU-ICSS,3D 图形

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参数

Arm MHz (Max.) 1100 Arm DMIPS 10120 Ethernet MAC 10/100/1000, 6-Port 10/100/1000 PRU EMAC Industrial protocols TSN, EtherCAT, EtherNet/IP, HSR, PRP, POWERLINK, PROFIBUS, PROFINET RT/IRT, SERCOS III Serial I/O CAN-FD, I2C, McASP, McSPI, SPI, UART, USB Camera MIPI CSI-2, Parallel DRAM DDR3L, DDR4, LPDDR4 Memory ECC Security enabler Cryptographic acceleration, Device identity, Secure boot, Debug security, External memory protection, Trusted execution environment, Networking security, Secure storage, Software IP protection, Initial secure programming, Secure FW and SW update Display MIPI DPI, OLDI Operating temperature range (C) -40 to 105 PCI/PCIe 2 PCIe Gen 3 Arm CPU 4 Arm Cortex-A53 open-in-new 查找其它 AM6x Arm Cortex-A53 处理器

封装|引脚|尺寸

FCBGA (ACD) 784 - open-in-new 查找其它 AM6x Arm Cortex-A53 处理器

特性

  • Processor cores:
  • Dual- or quad-core Arm® Cortex®-A53 microprocessor subsystem at up to 1.1 GHz
    • Up to two dual-core or two single-core Arm® Cortex®-A53 clusters with 512KB L2 cache including SECDED
    • Each A53 core has 32KB L1 ICache and 32K L1 DCache
  • Dual-core Arm® Cortex®-R5F at up to 400 MHz
    • Supports lockstep mode
    • 16KB ICache, 16KB DCache, and 64KB RAM per R5F core
  • Industrial subsystem:
  • Three gigabit Industrial Communication Subsystems (PRU_ICSSG)
    • Up to two 10/100/1000 Ethernet ports per PRU_ICSSG
    • Supports two SGMII ports (2)
    • Compatibility with 10/100Mb PRU-ICSS
    • 24× PWMs per PRU_ICSSG
      • Cycle-by-cycle control
      • Enhanced trip control
    • 18× Sigma-delta filters per PRU_ICSSG
      • Short circuit logic
      • Over-current logic
    • 6× Multi-protocol position encoder interfaces per PRU_ICSSG
  • Memory subsystem:
  • Up to 2MB of on-chip L3 RAM with SECDED
  • Multi-core Shared Memory Controller (MSMC)
    • Up to 2MB (2 banks × 1MB) SRAM with SECDED
      • Shared coherent Level 2 or Level 3 memory-mapped SRAM
      • Shared coherent Level 3 Cache
    • 256-bit processor port bus and 40-bit physical address bus
    • Coherent unified bi-directional interfaces to connect to processors or device masters
    • L2, L3 Cache pre-warming and post flushing
    • Bandwidth management with starvation bound
    • One infrastructure master interface
    • Single external memory master interface
    • Supports distributed virtual system
    • Supports internal DMA engine – Data Routing Unit (DRU)
    • ECC error protection
  • DDR Subsystem (DDRSS)
    • Supports DDR3L/DDR4 memory types up to DDR-1600
    • Supports LPDDR4 memory type up to DDR-1333
    • 32-bit data bus and 7-bit SECDED bus
    • 32GB of total addressable space
  • General-Purpose Memory Controller (GPMC)
  • SafeTI™ semiconductor component:
  • Designed for functional safety applications
  • Developed according to the requirements of IEC 61508
  • Achieves systematic integrity of SIL-3
  • For the MCU safety island, sufficient diagnostics are included to achieve random fault integrity requirements of SIL-2
  • For the rest of the SoC, sufficient diagnostics are included to achieve random fault integrity requirements of SIL-2
  • In addition, sufficient architectural metrics are in place to achieve execution of SIL-3 applications given a proper safety concept (for example reciprocal comparison by software)
  • Functional safety manual available
  • Safety-related certification
    • Component level functional safety certification by TÜV SÜD [certification in progress]
  • Functional safety features:
    • ECC or parity on calculation-critical memories and internal bus interconnect
    • Firewalls to help provide Freedom From Interference (FFI)
      • Built-In Self-Test (BIST) for CPU, high-end timers, and on-chip RAM
    • Hardware error injection support for test-for-diagnostics
    • Error Signaling Modules (ESM) for capture of functional safety related errors
    • Voltage, temperature, and clock monitoring
    • Windowed and non-windowed watchdog timers in multiple clock domains
  • MCU island
    • Isolation of the dual-core Arm® Cortex®-R5F microprocessor subsystem
    • Separate voltage, clocks, resets, and dedicated peripherals
    • Internal MCSPI connection to the rest of SoC
  • Security:
  • Secure boot supported
    • Hardware-enforced root-of-trust
    • Support to switch root-of-trust via backup key
    • Support for takeover protection, IP protection, and anti-roll back protection
  • Cryptographic acceleration supported
    • Session-aware cryptographic engine with ability to auto-switch key-material based on incoming data stream
    • Supports cryptographic cores
      • AES – 128/192/256 bits key sizes
      • 3DES – 56/112/168 bits key sizes
      • MD5, SHA1
      • SHA2 – 224/256/384/512
      • DRBG with true random number generator
      • PKA (public key accelerator) to assist in RSA/ECC processing
    • DMA support
  • Debugging security
    • Secure software controlled debug access
    • Security aware debugging
  • Trusted Execution Environment (TEE) supported
    • Arm® TrustZone® based TEE
    • Extensive firewall support for isolation
    • Secure DMA path and interconnect
    • Secure watchdog/timer/IPC
  • Secure storage support
  • On-the-fly encryption and authentication support for OSPI interface
  • Networking security support for data (payload) encryption/authentication via packet based hardware cryptographic engine
  • Security coprocessor (DMSC) for key and security management, with dedicated device level interconnect for security
  • SoC services:
  • Device Management Security Controller (DMSC)
    • Centralized SoC system controller
    • Manages system services including initial boot, security, functional safety and clock/reset/power management
    • Power management controller for active and low power modes
    • Communication with various processing units over message manager
    • Simplified interface for optimizing unused peripherals
    • Tracing and debugging capability
  • Sixteen 32-bit general-purpose timers
  • Two data movement and control Navigator Subsystems (NAVSS)
    • Ring Accelerator (RA)
    • Unified DMA (UDMA)
    • Up to 2 Timer Managers (TM) (1024 timers each)
  • Multimedia:
  • Display subsystem
    • Two fully input-mapped overlay managers associated with two display outputs
    • One port MIPI® DPI parallel interface
    • One port OLDI
  • PowerVR® SGX544-MP1 3D Graphics Processing Unit (GPU)
  • One Camera Serial Interface-2 (MIPI CSI-2)
  • One port video capture: BT.656/1120 (no embedded sync)
  • High-speed interfaces:
  • One Gigabit Ethernet (CPSW) interface supporting
    • RMII (10/100) or RGMII (10/100/1000)
    • IEEE1588 (2008 Annex D, Annex E, Annex F) with 802.1AS PTP
    • Audio/video bridging (P802.1Qav/D6.0)
    • Energy-efficient Ethernet (802.3az)
    • Jumbo frames (2024 bytes)
    • Clause 45 MDIO PHY management
  • Two PCI-Express® (PCIe®) revision 3.1 subsystems (2)
    • Supports Gen2 (5.0GT/s) operation
    • Two independent 1-lane, or a single 2-lane port
    • Support for concurrent root-complex and/or end-point operation
  • USB 3.1 Dual-Role Device (DRD) subsystem (2)
    • One enhanced SuperSpeed Gen1 port
    • One USB 2.0 port
    • Each port independently configurable as USB host, USB peripheral, or USB DRD
  • General connectivity:
  • 6× Inter-Integrated Circuit (I2C™) ports
  • 5× configurable UART/IrDA/CIR modules
  • Two simultaneous flash interfaces configured as
    • Two OSPI flash interfaces
    • or HyperBus™ and OSPI1 flash interface
  • 2× 12-bit Analog-to-Digital Converters (ADC)
    • Up to 4 Msamples/s
    • Eight multiplexed analog inputs
  • 8× Multichannel Serial Peripheral Interfaces (MCSPI) controllers
    • Two with internal connections
    • Six with external interfaces
  • General-Purpose I/O (GPIO) pins
  • Control interfaces:
  • 6× Enhanced High Resolution Pulse-Width Modulator (EHRPWM) modules
  • One Enhanced Capture (ECAP) module
  • 3× Enhanced Quadrature Encoder Pulse (EQEP) modules
  • Automotive interfaces:
  • 2× Modular Controller Area Network (MCAN) modules with full CAN-FD support
  • Audio interfaces:
  • 3× Multichannel Audio Serial Port (MCASP) modules
  • Media and data storage:
  • 2× Multimedia Card™/Secure Digital® (MMC™/SD®) interfaces
  • Simplified power management:
  • Simplified power sequence with full support for dual voltage I/O
  • Integrated LDOs reduces power solution complexity
  • Integrated SDIO LDO for handling automatic voltage transition for SD interface
  • Integrated Power On Reset (POR) generation reducing power solution complexity
  • Integrated voltage supervisor for functional safety monitoring
  • Integrated power supply glitch detector for detecting fast power supply transients
  • Analog/system integration:
  • Integrated USB VBUS detection
  • Fail safe I/O for DDR RESET
  • All I/O pins drivers disabled during reset to avoid bus conflicts
  • Default I/O pulls disabled during reset to avoid system conflicts
  • Support dynamic I/O pinmux configuration change
  • System-on-Chip (SoC) architecture:
  • Supports primary boot from UART, I2C, OSPI, HyperBus, parallel NOR Flash, SD or eMMC™, USB, PCIe, and Ethernet interfaces
  • 28-nm CMOS technology
  • 23 mm × 23 mm, 0.8-mm pitch, 784-pin FCBGA (ACD)

All trademarks are the property of their respective owners.

open-in-new 查找其它 AM6x Arm Cortex-A53 处理器

描述

AM654x and AM652x Sitara™ processors are Arm® applications processors built to meet the complex processing needs of modern industry 4.0 embedded products.

The AM654x and AM652x devices combine four or two Arm® Cortex®-A53 cores with a dual Arm® Cortex®-R5F MCU subsystem which includes features intended to help customers achieve their functional safety goals for their end products and three Gigabit industrial communications subsystems (PRU_ICSSG) to create a SoC capable of high-performance industrial controls with industrial connectivity and processing for functional safety applications. AM65xx is currently undergoing assessment to be certified by TÜV SÜD according to IEC 61508.

The four Arm® Cortex®-A53 cores in the AM654x are arranged in two dual-core clusters with shared L2 memory to create two processing channels. The two Arm® Cortex®-A53 cores in the AM652x are available in a single dual-core cluster and two single-core cluster options. Extensive ECC is included on on-chip memory, peripherals, and interconnect for reliability. The SoC as a whole includes features intended to help customers design systems that can achieve their functional safety goals (assessment pending with TÜV SÜD). Cryptographic acceleration and secure boot are available on some AM654x and AM652x devices in addition to granular firewalls managed by the DMSC.

Programmability is provided by the Arm® Cortex®-A53 RISC CPUs with Arm® Neon™ extension, and the dual Arm® Cortex®-R5F MCU subsystem is available for general purpose use as two cores or it can be used in lockstep to help meet the needs of functional safety applications. The PRU_ICSSG subsystems can be used to provide up to six ports of industrial Ethernet such as Profinet IRT, TSN, Ethernet/IP or EtherCAT® (among many others), or they can be used for standard Gigabit Ethernet connectivity.

TI provides a complete set of software and development tools for the Arm® cores including Processor SDK Linux, Linux-RT, RTOS, and Android as well as C compilers and a debugging interface for visibility into source code execution. Applicable functional safety and security documentation will be made available to assist customers in developing their functional safety or security related systems.

open-in-new 查找其它 AM6x Arm Cortex-A53 处理器
下载

更多信息

可提供原型样品 (X6580AACD)。立即申请

技术文档

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类型 标题 下载最新的英文版本 发布
* 勘误表 AM65x/DRA80xM Processors Silicon Revision 1.0 2019年 12月 23日
更多文献资料 电子书:工业机器人设计工程师指南 下载英文版本 2020年 3月 25日
更多文献资料 E-book: An engineer’s guide to industrial robot designs.. 2020年 3月 25日
应用手册 PRU-ICSS Feature Comparison 2020年 3月 9日
应用手册 AM65x/DRA80xM EMIF Tools 2020年 3月 4日
应用手册 AM65x/DRA80xM Silicon Revision 1.0 to 2.0 Migration Guide 2020年 1月 6日
用户指南 AM65x/DRA80xM Processors Technical Reference Manual 2019年 12月 18日
应用手册 AM65xx Time Synchronization Architecture 2019年 10月 14日
技术文章 Designing smarter remote terminal units for microgrids 2019年 10月 2日
应用手册 Programmable Logic Controllers — Security Threats and Solutions 2019年 9月 13日
技术文章 Solving synchronization challenges in Industrial Ethernet 2019年 7月 19日
应用手册 Enabling Android Automotive on Your TI Development Board 2019年 7月 12日
技术文章 Security versus functional safety: a view from the Processor Software Development Kit 2019年 5月 31日
白皮书 Utilizing Sitara™ processors for Industry 4.0 servo drives 2019年 5月 28日
应用手册 AM65x DDR ECC initialization and testing 2019年 3月 8日
应用手册 AM65x/DRA80xM DDR Board Design and Layout Guidelines 2019年 3月 7日
白皮书 Virtualization for embedded industrial systems 2019年 3月 7日
应用手册 Integrating a WiLink8 Module with the AM65x EVM 2019年 1月 29日
应用手册 PRU-ICSS Getting Started Guide on TI-RTOS 2019年 1月 18日
应用手册 PRU Read Latencies 2018年 12月 21日
应用手册 PRU-ICSS Getting Starting Guide on Linux 2018年 12月 10日
白皮书 Ensuring real-time predictability 2018年 12月 4日
应用手册 Jian will provide 2018年 11月 30日
白皮书 The state of functional safety in Industry 4.0 2018年 11月 27日
应用手册 PRU-ICSS / PRU_ICSSG Migration Guide 2018年 11月 5日
白皮书 适用于保护继电器的 Sitara AM6x 处理器 下载最新的英文版本 (Rev.A) 2018年 10月 24日
白皮书 EtherNet/IP on TI's Sitara AM335x Processors 2018年 10月 13日
白皮书 Secure Boot on embedded Sitara™ processors 2018年 10月 13日
应用手册 Sitara Processor Power Distribution Networks: Implementation and Analysis 2018年 10月 12日
白皮书 Designing industrial controls for Industry 4.0 with Sitara™ AM6x processors 2018年 10月 11日
应用手册 Hardware Design Guide for AM65x/DRA80xM Devices 2018年 10月 11日
应用手册 AM65x Schematic Checklist 2018年 10月 4日
技术文章 Simplified software development through the Processor SDK and tools 2018年 10月 2日
白皮书 Time sensitive networking for industrial automation 2018年 10月 2日
用户指南 AM654x BGA Escape Routing Stackup 2018年 8月 29日
白皮书 Designing Embedded Systems for High Reliability With Sitara AM6x Processors 2018年 8月 28日

设计与开发

有关其他条款或所需资源,请点击下面的任何链接来查看详情页面。

硬件开发

评估板 下载
$199.00
说明

1280 x 800 LCD 显示附件套件是一款用于 AM65x IDK (TMDX654IDKEVM) 的附加附件,增加了触摸和显示功能,适用于 HMI 和工业 PC 评估以及其他需要显示器的用例。1280 x 800 LCD 显示附件套件带有 AM65x EVM (TMDX654GPEVM),但也可以作为替代品单独出售。此 LCD 屏幕为 10.1" 显示屏,具有 WXGA 分辨率 (1280 x 800) 并支持 10 点电容式触摸。

特性
硬件

10.1" LCD 屏幕 (1280 x 800)
评估板 下载
document-generic 用户指南
$898.00
说明

The AM65x Evaluation Module provides a platform to quickly start evaluation of Sitara™ Arm® Cortex®-A53 AM65x Processors (AM6548AM6546AM6528AM6527AM6526) and accelerate development for HMI, networking, patient monitoring, and other industrial applications. It is a development platform based on (...)

特性
  • 3 gigabit Ethernet ports
  • 4GB DDR4 with ECC
  • On-board 16GB eMMC
  • On-board 512Mb OSPI Flash
  • 1-lane PCIe Gen3.1, USB 3.1, USB 2.0 and CSI-2 interfaces
评估板 下载
document-generic 用户指南
$1,369.00
说明
AM65x 高安全性 (HS) 评估模块提供了平台,用于评估 Sitara™ Arm® Cortex®-A53 AM65x 处理器(AM6548、AM6546、AM6528、AM6527、AM6526)的安全引导和其他安全特性。它是基于四核 Cortex-A53、双 Cortex-R5F 处理器的开发平台,集成有 PCIe、USB 3.0/2.0、千兆以太网等各种连接选项。
特性
  • 3 个千兆以太网端口
  • 具备 ECC 保护的 4GB DDR4
  • 板载 16GB eMMC
  • 车载 512MB OSPI 闪存
  • 单通道 PCIe 第 3.1 代、USB 3.1、USB 2.0 和 CSI-2 接口
评估板 下载
document-generic 用户指南
$819.00
说明

AM65x 工业开发套件 (IDK) 是用于评估 Sitara AM65x 处理器的工业通信和控制功能的开发平台,适用于工厂自动化、驱动器、机器人、电网基础设施等领域的应用。AM65x 处理器包含三个 PRU-ICSS(适用于工业通信的可编程实时单元)子系统,该子系统可用于 Profinet、EtherCAT、以太网/IP 等千兆工业以太网协议。

特性
  • 可同时使用最多 6 个工业千兆以太网端口和 1 个标准千兆以太网端口
  • 具备 ECC 保护的 4GB DDR4
  • Profibus 连接和工业 I/O 接头
  • 板载 16GB eMMC
  • 板载 512Mb OSPI 闪存
  • 2 通道 PCIe 第 3.1 代、USB 2.0 和 CSI-2 接口
评估板 下载
Mistral Solutions AM65x System on Module (SOM)
由 Mistral Solutions Pvt. Ltd 提供
说明

The AM65x SOM from Mistral is an easy to use, compact, light-weight system on module (SOM) providing very high processing power for industrial applications. This module is based on Texas Instruments Sitara™ AM6548 SoC and is ideal for complex processing, connectivity and control required for (...)

评估板 下载
说明

phyCORE®-AM65x 模块为 phyCORE® 系列带来了安全启动、多协议千兆位工业通信、图形和功能安全特性以及时间敏感型网络 (TSN)。phyCORE®-AM65x SOM 是工业通信系统、工厂自动化、边缘计算、电网基础设施和需要高可靠性的应用的理想选择。利用四个 Arm® Cortex®-A53 内核来运行您的应用,6 个工业 PRU 接口用于支持时间敏感型通信协议,隔离的两个 Cortex®-R5F 内核用于提供功能安全支持。

PHYTEC 是引领行业的模块上系统 (SOM)、嵌入式中间件和设计服务提供商与集成商,可帮助客户轻松地快速将复杂产品推向市场。借助于深厚的专业知识、高质量产品、供应链专业知识以及灵活、协作的实践,我们会在从设计到生产的整个过程中为客户提供指导。在公司内部组装部门与外部生产合作伙伴的支持下,不论您的订单量是大是小,PHYTEC 均可提供定制解决方案。

30 多年来,我们一直为众多行业的客户提供 SOM 及相关硬件、软件、套件和设计服务。这些解决方案使我们的顾客能够缩短产品上市时间,降低开发成本及设计风险。通过与 TI 的战略联盟,PHYTEC 为 Sitara 处理器以及其他 TI 器件提供占得市场先机的解决方案。

PHYTEC 是 TI 第三方网络的成员,总部位于德国美因茨,在美国、法国、中国和印度设有分支机构。

有关 PHYTEC 的更多信息,请访问 www.phytec.com

特性
  • DDR4 + 可选 ECC
  • 高达 32GB eMMC
  • 可选 2.4GHz 或 5GHz 认证 WiFi 解决方案
  • 1x 10/100/1000 Mb/s + 6 PRU-ICSSG
  • Linux、Android 和 TI-RTOS BSP

软件开发

软件开发套件 (SDK) 下载
适用于 AM65x Sitara 处理器的处理器 SDK(支持 Linux、TI-RTOS 和 Android)
PROCESSOR-SDK-AM65X 处理器 SDK(软件开发套件)是统一的软件平台,适用于 TI 嵌入式处理器,设置简单,提供开箱即用的基准测试和演示。处理器 SDK 的所有版本在 TI 的广泛产品系列中保持一致,让开发人员可以无缝地在多种器件之间重用和迁移软件。处理器 SDK 和 TI 的嵌入式处理器解决方案让可扩展平台解决方案的开发变得前所未有的简单。

处理器 SDK 支持 Linux 和 TI-RTOS 操作系统。

Linux 亮点:

  • 长期稳定 (LTS) Linux 内核支持
  • U-Boot 引导加载程序支持
  • Linaro GNU Compiler Collection (GCC) 工具链
  • 兼容 Yocto Project™ OE Core 的文件系统

RTOS 亮点:

  • TI-RTOS 内核,一种用于 TI 器件的轻量级实时嵌入式操作系统
  • 芯片支持库、驱动程序和基本的板级支持实用程序
  • 用于多个核心和器件之间通信的处理器间通信
  • 基本的网络堆栈和协议
  • 引导加载程序和引导实用程序
  • Linaro GNU Compiler Collection (GCC) 工具链

Linaro 工具链支持

Linaro 工具链包括强大的商用级工具,这些工具专门针对 Cortex-A 处理器进行了优化。此工具链得到了 TI 和整个 Linaro 社区的全力支持,包括来自 Linaro 内部工程师、成员公司开发者以及开源社区的其他人员的支持。此最新版处理器 SDK 中包含 Linaro 工具、软件和测试过程。

Yocto Project™ 支持

Yocto 项目是由 (...)

特性

Linux 特性

  • 开放的 Linux 支持
  • Linux 内核和引导加载程序
  • 文件系统
  • Qt/Webkit 应用程序框架
  • 3D 图形支持
  • 基于 GUI 的应用程序启动器
  • 示例应用
  • ARM 基准测试:Dhrystone、Linpack、Whetstone
  • Webkit Web 浏览器
  • 可编程实时单元 (PRU)
  • 主机工具,包括闪存工具和引脚复用实用程序
  • 用于 Linux 开发的 Code Composer Studio™ IDE
  • 文档

RTOS 特性

  • 提供驱动程序
  • 文件系统
  • 裸机次级引导加载程序
  • 调试和仪表实用程序
  • 板级支持包和诊断功能
  • 示例应用
  • 主机工具,包括引脚复用和时钟树实用程序
  • 用于 RTOS 开发的 Code Composer Studio™ IDE
  • 文档

 

处理器 SDK 完全免费,无需向德州仪器 (TI) 支付任何运行时版税。
应用软件和框架 下载
Sitara 外部存储器接口 (EMIF) 工具
SITARA-DDR-CONFIG-TOOL Sitara™ EMIF 工具是一款软件工具,提供用于配置 TI 处理器以访问外部 DDR 存储器器件的接口。该工具还对延迟锁定环路 (DLL) 设置进行优化,以补偿电路板布线偏斜。结果会作为 EMIF 配置寄存器进行输出,可将其导出以在处理器 SDK、Code Composer Studio 或定制软件中使用。  
特性
  • 支持器件上可用的所有 DDR 存储器类型(LPDDR2、DDR3 和 DDR3L DDR)
  • 支持 DDR3/3L 硬件矫正
  • 根据 JEDEC 标准对 DRAM 时序进行错误检查
  • 输出 EMIF 配置寄存器,可以在处理器 SDK 和 Code Composer Studio 中直接使用它们
IDE、配置、编译器和调试器 下载
适用于 Sitara™ 处理器的 Code Composer Studio (CCS) 集成开发环境 (IDE)
CCSTUDIO-SITARA

Download the latest version of Code Composer Studio

Code Composer Studio™ - Integrated Development Environment for Sitara™ ARM© Processors

 

Code Composer Studio is an integrated development environment (IDE) that supports TI's Microcontroller and Embedded Processors portfolio. Code Composer Studio comprises a suite of tools used to develop and debug (...)

IDE、配置、编译器和调试器 下载
SafeTI™ 编译器资质审核套件
SAFETI_CQKIT 为帮助客户验证 TI ARM、C6000 或 C2000/CLA C/C++ 编译器符合 IEC 61508 和 ISO 26262 等功能安全标准,我们开发了 SafeTI 编译器资质审核套件。

SafeTI 编译器资质审核套件:

  • 无需用户运行资质审核测试
  • 支持编译器覆盖范围分析
  • 不包括 Validas 咨询
  • 面向 TI 客户免费提供

要获取 SafeTI 编译器资质审核套件,请单击上方相应的申请按钮。

请访问 www.ti.com/safeti,了解更多有关功能安全产品的信息

必要条件

SafeTI 编译器资质审核套件仅适用于 TI C/C++ 编译器的长期支持 (LTS) 版本,而且不设其他必要条件

特性

SafeTI 编译器资质审核套件经 TÜV Nord 评估符合 IEC 61508 和 ISO 26262 标准,并且是与专门从事软件工具资质审核的咨询公司 Validas 协作开发的。

包含项目

SafeTI 编译器资质审核套件包括:

  • 安全文档模板
    • 工具分类
    • 工具资质审核计划
    • 工具资质审核报告
    • 工具安全手册
  • QKIT 用户指南
  • TÜV Nord 批准报告
  • 内部版本验证结果
  • 仪器化编译器

设计工具和仿真

仿真模型 下载
SPRM718.ZIP (2 KB) - Thermal Model
仿真模型 下载
SPRM724.ZIP (12 KB) - BSDL Model
仿真模型 下载
SPRM737.ZIP (19753 KB) - IBIS Model
计算工具 下载
Clock Tree Tool for Sitara™ ARM® Processors
CLOCKTREETOOL The Clock Tree Tool (CTT) for Sitara™ ARM®, Automotive, and Digital Signal Processors is an interactive clock tree configuration software that provides information about the clocks and modules in these TI devices. It allows the user to:
  • Visualize the device clock tree
  • Interact with clock tree elements (...)
document-generic 用户指南
计算工具 下载

CAD/CAE 符号

封装 引脚 下载
FCBGA (ACD) 784 视图选项

订购与质量

支持与培训

可获得 TI E2E™ 论坛的工程师技术支持

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如果您对质量、包装或订购 TI 产品有疑问,请参阅 TI 支持