主页 微控制器 (MCU) 和处理器 基于 Arm 的处理器
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微控制器 (MCU) 和处理器
基于 Arm 的处理器
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TDA4VL-Q1

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具有 AI 和图形、适用于环视泊车辅助应用的汽车片上系统

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TDA4VL-Q1

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产品详情

Arm CPU 2 Arm Cortex-A72 Arm (max) (MHz) 1200 Coprocessors 2 Arm Cortex-R5F, MCU Island of 1 Dual Arm Cortex-R5 CPU 64-bit Graphics acceleration 1 3D Display type 1 DSI, 1 EDP, MIPI DPI Protocols Ethernet Ethernet MAC 2-Port 10/100/1000 PCIe 1 PCIe Gen 3 Hardware accelerators 1 Deep learning accelerator, 1 Depth and Motion accelerator, 1 Vision Processing accelerator, 1 video encode/decode accelerator Features Multimedia, Vision Analytics Operating system Linux, QNX, RTOS Rating Automotive Operating temperature range (°C) -40 to 125
Arm CPU 2 Arm Cortex-A72 Arm (max) (MHz) 1200 Coprocessors 2 Arm Cortex-R5F, MCU Island of 1 Dual Arm Cortex-R5 CPU 64-bit Graphics acceleration 1 3D Display type 1 DSI, 1 EDP, MIPI DPI Protocols Ethernet Ethernet MAC 2-Port 10/100/1000 PCIe 1 PCIe Gen 3 Hardware accelerators 1 Deep learning accelerator, 1 Depth and Motion accelerator, 1 Vision Processing accelerator, 1 video encode/decode accelerator Features Multimedia, Vision Analytics Operating system Linux, QNX, RTOS Rating Automotive Operating temperature range (°C) -40 to 125
FCBGA (ALZ) 770 529 mm² 23 x 23

Processor cores:

  • Two C7x floating point, vector DSP, up to 1.0 GHz, 160 GFLOPS, 512 GOPS
  • Deep-learning matrix multiply accelerator (MMA), up to 8 TOPS (8b) at 1.0 GHz
  • Vision Processing Accelerators (VPAC) with Image Signal Processor (ISP) and multiple vision assist accelerators
  • Depth and Motion Processing Accelerators (DMPAC)
  • Dual 64-bit Arm Cortex-A72 microprocessor subsystem at up to 2 GHz
    • 1MB shared L2 cache per dual-core Cortex-A72 cluster
    • 32KB L1 DCache and 48KB L1 ICache per Cortex-A72 core
  • Up to Six Arm Cortex-R5F MCUs at up to 1.0 GHz
    • 16K I-Cache, 16K D-Cache, 64K L2 TCM
    • Two Arm Cortex-R5F MCUs in isolated MCU subsystem
    • Four (TDA4VE) or Two (TDA4AL/TDA4VL)Arm Cortex-R5F MCUs in general compute partition
  • GPU IMG BXS-64-4, 256kB Cache, up to 800 MHz, 50 GFLOPS, 4 GTexels/s (TDA4VE and TDA4VL)
  • Custom-designed interconnect fabric supporting near max processing entitlement

Memory subsystem:

  • Up to 4MB of on-chip L3 RAM with ECC and coherency
    • ECC error protection
    • Shared coherent cache
    • Supports internal DMA engine
  • Up to Two External Memory Interface (EMIF) modules with ECC
    • Supports LPDDR4 memory types
    • Supports speeds up to 4266 MT/s
    • Two (TDA4VE) or One (TDA4AL/TDA4VL) 32-bit data bus with inline ECC up to 17 GB/s per EMIF
  • General-Purpose Memory Controller (GPMC)
  • One (TDA4AL/TDA4VL) or Two (TDA4VE) 512KB on-chip SRAM in MAIN domain, protected by ECC

Functional Safety:

  • Functional Safety-Compliant targeted (on select part numbers)
  • Developed for functional safety applications
  • Documentation available to aid ISO 26262 functional safety system design up to ASIL-D/SIL-3 targeted
  • Systematic capability up to ASIL-D/SIL-3 targeted
  • Hardware integrity up to ASIL-D/SIL-3 targeted for MCU Domain
  • Hardware integrity up to ASIL-B/SIL-2 targeted for Main Domain
  • Hardware integrity up to ASIL-D/SIL-3 targeted for Extended MCU (EMCU) portion of the Main Domain
  • Safety-related certification
    • ISO 26262 planned

Device security (on select part numbers):

  • Secure boot with secure runtime support
  • Customer programmable root key, up to RSA-4K or ECC-512
  • Embedded hardware security module
  • Crypto hardware accelerators – PKA with ECC, AES, SHA, RNG, DES and 3DES

High speed serial interfaces:

  • One PCI-Express (PCIe) Gen3 controllers
    • Up to four lanes per controller
    • Gen1 (2.5GT/s), Gen2 (5.0GT/s), and Gen3 (8.0GT/s) operation with auto-negotiation
  • One USB 3.0 dual-role device (DRD) subsystem
    • Enhanced SuperSpeed Gen1 Port
    • Supports Type-C switching
    • Independently configurable as USB host, USB peripheral, or USB DRD
  • Two CSI2.0 4L RX plus Two CSI2.04L TX

Automotive interfaces:

  • Twenty Modular Controller Area Network (MCAN) modules with full CAN-FD support

Display subsystem:

  • One (TDA4AL/TDA4VL) or Two (TDA4VE) DSI 4L TX (up to 2.5K)
  • One eDP 4L (TDA4VE/TDA4VL)
  • One DPI

Audio interfaces:

  • Five Multichannel Audio Serial Port (MCASP) modules

Video acceleration:

  • TDA4VE: H.264/H.265 Encode/Decode (up to 480 MP/s)
  • TDA4AL: H.264/H.265 Encode only (up to 480 MP/s)
  • TDA4VL: H.264/H.265 Encode/Decode (up to 240 MP/s)

Ethernet:

  • Two RMII/RGMII interfaces

Flash memory interfaces:

  • Embedded MultiMediaCard Interface ( eMMC™ 5.1)
  • One Secure Digital 3.0/Secure Digital Input Output 3.0 interfaces (SD3.0/SDIO3.0)
  • Two simultaneous flash interfaces configured as
    • One OSPI or HyperBus™ or QSPI, and
    • One QSPI

System-on-Chip (SoC) architecture:

  • 16-nm FinFET technology
  • 23 mm x 23 mm, 0.8-mm pitch, 770-pin FCBGA (ALZ)

Companion Power Management ICs (PMIC):

  • Functional Safety-Compliant support up to ASIL-D / SIL-3 targeted
  • Flexible mapping to support different use cases

Processor cores:

  • Two C7x floating point, vector DSP, up to 1.0 GHz, 160 GFLOPS, 512 GOPS
  • Deep-learning matrix multiply accelerator (MMA), up to 8 TOPS (8b) at 1.0 GHz
  • Vision Processing Accelerators (VPAC) with Image Signal Processor (ISP) and multiple vision assist accelerators
  • Depth and Motion Processing Accelerators (DMPAC)
  • Dual 64-bit Arm Cortex-A72 microprocessor subsystem at up to 2 GHz
    • 1MB shared L2 cache per dual-core Cortex-A72 cluster
    • 32KB L1 DCache and 48KB L1 ICache per Cortex-A72 core
  • Up to Six Arm Cortex-R5F MCUs at up to 1.0 GHz
    • 16K I-Cache, 16K D-Cache, 64K L2 TCM
    • Two Arm Cortex-R5F MCUs in isolated MCU subsystem
    • Four (TDA4VE) or Two (TDA4AL/TDA4VL)Arm Cortex-R5F MCUs in general compute partition
  • GPU IMG BXS-64-4, 256kB Cache, up to 800 MHz, 50 GFLOPS, 4 GTexels/s (TDA4VE and TDA4VL)
  • Custom-designed interconnect fabric supporting near max processing entitlement

Memory subsystem:

  • Up to 4MB of on-chip L3 RAM with ECC and coherency
    • ECC error protection
    • Shared coherent cache
    • Supports internal DMA engine
  • Up to Two External Memory Interface (EMIF) modules with ECC
    • Supports LPDDR4 memory types
    • Supports speeds up to 4266 MT/s
    • Two (TDA4VE) or One (TDA4AL/TDA4VL) 32-bit data bus with inline ECC up to 17 GB/s per EMIF
  • General-Purpose Memory Controller (GPMC)
  • One (TDA4AL/TDA4VL) or Two (TDA4VE) 512KB on-chip SRAM in MAIN domain, protected by ECC

Functional Safety:

  • Functional Safety-Compliant targeted (on select part numbers)
  • Developed for functional safety applications
  • Documentation available to aid ISO 26262 functional safety system design up to ASIL-D/SIL-3 targeted
  • Systematic capability up to ASIL-D/SIL-3 targeted
  • Hardware integrity up to ASIL-D/SIL-3 targeted for MCU Domain
  • Hardware integrity up to ASIL-B/SIL-2 targeted for Main Domain
  • Hardware integrity up to ASIL-D/SIL-3 targeted for Extended MCU (EMCU) portion of the Main Domain
  • Safety-related certification
    • ISO 26262 planned

Device security (on select part numbers):

  • Secure boot with secure runtime support
  • Customer programmable root key, up to RSA-4K or ECC-512
  • Embedded hardware security module
  • Crypto hardware accelerators – PKA with ECC, AES, SHA, RNG, DES and 3DES

High speed serial interfaces:

  • One PCI-Express (PCIe) Gen3 controllers
    • Up to four lanes per controller
    • Gen1 (2.5GT/s), Gen2 (5.0GT/s), and Gen3 (8.0GT/s) operation with auto-negotiation
  • One USB 3.0 dual-role device (DRD) subsystem
    • Enhanced SuperSpeed Gen1 Port
    • Supports Type-C switching
    • Independently configurable as USB host, USB peripheral, or USB DRD
  • Two CSI2.0 4L RX plus Two CSI2.04L TX

Automotive interfaces:

  • Twenty Modular Controller Area Network (MCAN) modules with full CAN-FD support

Display subsystem:

  • One (TDA4AL/TDA4VL) or Two (TDA4VE) DSI 4L TX (up to 2.5K)
  • One eDP 4L (TDA4VE/TDA4VL)
  • One DPI

Audio interfaces:

  • Five Multichannel Audio Serial Port (MCASP) modules

Video acceleration:

  • TDA4VE: H.264/H.265 Encode/Decode (up to 480 MP/s)
  • TDA4AL: H.264/H.265 Encode only (up to 480 MP/s)
  • TDA4VL: H.264/H.265 Encode/Decode (up to 240 MP/s)

Ethernet:

  • Two RMII/RGMII interfaces

Flash memory interfaces:

  • Embedded MultiMediaCard Interface ( eMMC™ 5.1)
  • One Secure Digital 3.0/Secure Digital Input Output 3.0 interfaces (SD3.0/SDIO3.0)
  • Two simultaneous flash interfaces configured as
    • One OSPI or HyperBus™ or QSPI, and
    • One QSPI

System-on-Chip (SoC) architecture:

  • 16-nm FinFET technology
  • 23 mm x 23 mm, 0.8-mm pitch, 770-pin FCBGA (ALZ)

Companion Power Management ICs (PMIC):

  • Functional Safety-Compliant support up to ASIL-D / SIL-3 targeted
  • Flexible mapping to support different use cases

The TDA4VE TDA4AL TDA4VL processor family is based on the evolutionary Jacinto™ 7 architecture, targeted at Smart Vision Camera applications and built on extensive market knowledge accumulated over a decade of TI’s leadership in the Vision processor market. The TDA4AL provides high performance compute for both traditional and deep learning algorithms at industry leading power/performance ratios with a high level of system integration to enable scalability and lower costs for advanced vision camera applications. Key cores include next generation DSP with scalar and vector cores, dedicated deep learning and traditional algorithm accelerators, latest Arm and GPU processors for general compute, an integrated next generation imaging subsystem (ISP), video codec, and isolated MCU island. All protected by automotive grade safety and security hardware accelerators.

Key Performance Cores Overview: The “C7x” next generation DSP combines TI’s industry leading DSP and EVE cores into a single higher performance core and adds floating-point vector calculation capabilities, enabling backward compatibility for legacy code while simplifying software programming. The new “MMA” deep learning accelerator enables performance up to 8 TOPS within the lowest power envelope in the industry when operating at the typical automotive worst case junction temperature of 125°C. The dedicated Vision hardware accelerators provide vision pre-processing with no impact on system performance.

General Compute Cores and Integration Overview: Separate dual core cluster configuration of Arm® Cortex®-A72 facilitates multi-OS applications with minimal need for a software hypervisor. Up to four Arm® Cortex®-R5F subsystems enable low-level, timing critical processing tasks to leave the Arm® Cortex®-A72 core’s unencumbered for applications. Building on the existing world-class ISP, TI’s 7th generation ISP includes flexibility to process a broader sensor suite, support for higher bit depth, and features targeting analytics applications. Integrated diagnostics and safety features support operations up to ASIL-D levels while the integrated security features protect data against modern day attacks. CSI2.0 ports enable multi sensor inputs. To further the integration, the TDA4VE TDA4AL TDA4VL family also includes an MCU island eliminating the need for an external system microcontroller.

The TDA4VE TDA4AL TDA4VL processor family is based on the evolutionary Jacinto™ 7 architecture, targeted at Smart Vision Camera applications and built on extensive market knowledge accumulated over a decade of TI’s leadership in the Vision processor market. The TDA4AL provides high performance compute for both traditional and deep learning algorithms at industry leading power/performance ratios with a high level of system integration to enable scalability and lower costs for advanced vision camera applications. Key cores include next generation DSP with scalar and vector cores, dedicated deep learning and traditional algorithm accelerators, latest Arm and GPU processors for general compute, an integrated next generation imaging subsystem (ISP), video codec, and isolated MCU island. All protected by automotive grade safety and security hardware accelerators.

Key Performance Cores Overview: The “C7x” next generation DSP combines TI’s industry leading DSP and EVE cores into a single higher performance core and adds floating-point vector calculation capabilities, enabling backward compatibility for legacy code while simplifying software programming. The new “MMA” deep learning accelerator enables performance up to 8 TOPS within the lowest power envelope in the industry when operating at the typical automotive worst case junction temperature of 125°C. The dedicated Vision hardware accelerators provide vision pre-processing with no impact on system performance.

General Compute Cores and Integration Overview: Separate dual core cluster configuration of Arm® Cortex®-A72 facilitates multi-OS applications with minimal need for a software hypervisor. Up to four Arm® Cortex®-R5F subsystems enable low-level, timing critical processing tasks to leave the Arm® Cortex®-A72 core’s unencumbered for applications. Building on the existing world-class ISP, TI’s 7th generation ISP includes flexibility to process a broader sensor suite, support for higher bit depth, and features targeting analytics applications. Integrated diagnostics and safety features support operations up to ASIL-D levels while the integrated security features protect data against modern day attacks. CSI2.0 ports enable multi sensor inputs. To further the integration, the TDA4VE TDA4AL TDA4VL family also includes an MCU island eliminating the need for an external system microcontroller.
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设计和开发

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调试探针

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软件开发套件 (SDK)

PROCESSOR-SDK-LINUX-J721S2 — Linux® SDK for TDA4VE, TDA4VL and TDA4AL

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支持的产品和硬件

支持的产品和硬件

产品
基于 Arm 的处理器
TDA4AL-Q1 — 通过摄像头和雷达传感器实现前置摄像头和 ADAS 域控制的汽车片上系统 TDA4VE-Q1 — 通过 AI 实现自动泊车和驾驶辅助、具有视觉预处理和 GPU 的汽车片上系统 TDA4VL-Q1 — 具有 AI 和图形、适用于环视泊车辅助应用的汽车片上系统
硬件开发
评估板
J721S2XSOMXEVM — TDA4VE-Q1、TDA4VL-Q1 和 TDA4AL-Q1 模块上系统 (SoM)
下载选项
软件开发套件 (SDK)

PROCESSOR-SDK-QNX-J721S2 — QNX SDK for TDA4VE, TDA4VL and TDA4AL

The J721S2 processor software development kit (SDK) real-time operating system (RTOS) can be used together with either processor SDK Linux® or processor SDK QNX® to form a multiprocessor software development platform for TDA4VL-Q1 and TDA4AL-Q1 system-on-a-chip (SoCs) within our Jacinto™ platform.

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支持的产品和硬件

支持的产品和硬件

产品
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TDA4AL-Q1 — 通过摄像头和雷达传感器实现前置摄像头和 ADAS 域控制的汽车片上系统 TDA4VE-Q1 — 通过 AI 实现自动泊车和驾驶辅助、具有视觉预处理和 GPU 的汽车片上系统 TDA4VL-Q1 — 具有 AI 和图形、适用于环视泊车辅助应用的汽车片上系统
硬件开发
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软件开发套件 (SDK)

PROCESSOR-SDK-RTOS-J721S2 — RTOS SDK for TDA4VE, TDA4VL and TDA4AL

The J721S2 processor software development kit (SDK) real-time operating system (RTOS) can be used together with either processor SDK Linux® or processor SDK QNX® to form a multiprocessor software development platform for TDA4VL-Q1 and TDA4AL-Q1 system-on-a-chip (SoCs) within our Jacinto™ platform.

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支持的产品和硬件

支持的产品和硬件

产品
基于 Arm 的处理器
TDA4AL-Q1 — 通过摄像头和雷达传感器实现前置摄像头和 ADAS 域控制的汽车片上系统 TDA4VE-Q1 — 通过 AI 实现自动泊车和驾驶辅助、具有视觉预处理和 GPU 的汽车片上系统 TDA4VL-Q1 — 具有 AI 和图形、适用于环视泊车辅助应用的汽车片上系统
硬件开发
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IDE、配置、编译器或调试器

C7000-CGT — C7000 代码生成工具 - 编译器

TI C7000 C/C++ 编译器工具支持开发适用于 TI C7000 数字信号处理器内核的应用。

Code Composer Studio 是适用于 TI 嵌入式器件的集成开发环境 (IDE)。如果您希望在 TI 嵌入式器件上进行开发，建议先下载 Code Composer Studio。C7000 编译器通常与软件开发套件 (SDK) 一起提供，也可作为 Code Composer Studio 的更新提供。如果您已经是 Code Composer Studio 的用户，则更新编译器的理想方法是转到“Help”菜单并选择安装编译器（有关更多详细信息，请参阅在 CCS 中获取编译器更新）。
用户指南: PDF | HTML
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CCSTUDIO — Code Composer Studio 集成式开发环境 (IDE)

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支持的产品和硬件

支持的产品和硬件

此设计资源支持这些类别中的大部分产品。

查看产品详情页，验证是否能提供支持。

产品
汽车毫米波雷达传感器
AWR1243 — 76GHz 至 81GHz 高性能汽车类 MMIC AWR1443 — 集成 MCU 和硬件加速器的单芯片 76GHz 至 81GHz 汽车雷达传感器 AWR1642 — 集成 DSP 和 MCU 的单芯片 76GHz 至 81GHz 汽车雷达传感器 AWR1843 — 集成 DSP、MCU 和雷达加速器的单芯片 76GHz 至 81GHz 汽车雷达传感器 AWR1843AOP — Single-chip 76-GHz to 81-GHz automotive radar sensor integrating antenna on package, DSP and MCU AWR2243 — 76GHz 至 81GHz 汽车类第二代高性能 MMIC AWR2944 — 适用于角雷达和远距离雷达的汽车类第二代 76GHz 至 81GHz 高性能 SoC AWR6443 — Single-chip 60-GHz to 64-GHz automotive radar sensor integrating MCU and radar accelerator AWR6843 — 集成 DSP、MCU 和雷达加速器的单芯片 60GHz 至 64GHz 汽车雷达传感器 AWR6843AOP — 集成封装天线、DSP 和 MCU 的单芯片 60GHz 至 64GHz 汽车雷达传感器
工业毫米波雷达传感器
IWR1443 — 集成 MCU 和硬件加速器的 76GHz 至 81GHz 单芯片毫米波传感器 IWR1642 — 集成 DSP 和 MCU 的 76GHz 至 81GHz 单芯片毫米波传感器 IWR1843 — 集成 DSP、MCU 和雷达加速器的 76GHz 至 81GHz 单芯片工业雷达传感器 IWR6443 — 集成 MCU 和硬件加速器的 60GHz 至 64GHz 单芯片毫米波传感器 IWR6843 — 集成有处理功能的 60GHz 至 64GHz 单芯片智能毫米波传感器 IWR6843AOP — 具有集成封装天线 (AoP) 的单芯片 60GHz 至 64GHz 智能毫米波传感器
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IDE、配置、编译器或调试器

SAFETI_CQKIT — 安全编译器资质审核套件

为帮助客户验证 TI ARM、C6000、C7000 或 C2000/CLA C/C++ 编译器符合 IEC 61508 和 ISO 26262 等功能安全标准，我们开发了 SafeTI 编译器资质审核套件。

SafeTI 编译器资质审核套件：

  • 面向 TI 客户免费提供
  • 无需用户运行资质审核测试
  • 支持编译器覆盖范围分析*
    • * 可从每个 QKIT 下载页面下载覆盖数据收集说明。
  • 不包括 Validas 咨询

要获取 SafeTI 编译器资质审核套件，请点击上方相应的申请按钮。

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IDE、配置、编译器或调试器

SYSCONFIG — 系统配置工具

SysConfig 是一款配置工具，旨在简化硬件和软件配置挑战，从而加速软件开发。

SysConfig 可作为 Code Composer Studio™ 集成开发环境的一部分以及作为独立应用提供。此外，可以通过访问 TI 开发人员专区，在云中运行 SysConfig。

SysConfig 提供直观的图形用户界面，用于配置引脚、外设、无线电、软件栈、RTOS、时钟树和其他元件。SysConfig 将自动检测、发现和解决冲突，来加快软件开发。

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软件编程工具

TI-EDGE-AI-CLOUD — 针对 Jacinto 处理器上 AI 推理的云工具评估

TI Edge AI Cloud 是一项免费在线服务，可用于评估 TDA4x 处理器的加速深度学习推理性能。您不需要购买评估板。该服务基于 Python；只需几分钟即可登录、部署模型并获得各种性能基准。

使用业界通用 API（包括 TensorFlow Lite、ONNX Runtime、TVM、GStreamer、Docker、ROS 和 OpenGL ES）轻松编译和部署模型并加速推理。无需使用手动工具即可加速 TDA4x 处理器的深度学习推理性能。

在云中评估
设计工具

PROCESSORS-3P-SEARCH — 基于 Arm® 的 MPU、基于 Arm 的 MCU 和 DSP 第三方搜索工具

TI 已与多家公司合作，提供各种使用 TI 处理器的软件、工具和 SOM，从而加快您的量产速度。下载此搜索工具，快速浏览我们的第三方解决方案，并寻找合适的第三方来满足您的需求。此处所列的软件、工具和模块由独立的第三方生产和管理，而非德州仪器 (TI)。

搜索工具按产品类型划分为以下类别：

  • 工具包括 IDE/编译器、调试和跟踪、仿真和建模软件以及闪存编程器。
  • 操作系统包括 TI 处理器支持的操作系统。
  • 应用软件是指应用特定的软件，包括在 TI 处理器上运行的中间件和库。
  • SoM 是模块上系统解决方案
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FCBGA (ALZ) 770 了解详情

订购和质量

包含信息：
  • RoHS
  • REACH
  • 器件标识
  • 引脚镀层/焊球材料
  • MSL 等级/回流焊峰值温度
  • MTBF/时基故障估算
  • 材料成分
  • 认证摘要
  • 持续可靠性监测

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