This article applies to the following devices:

• AM6548
• AM6546
• AM6528
• AM6527
• AM6526
• DRA804M
• DRA802M

Links to TI hardware designs based on AM65x:

• AM654x General Purpose EVM
• AM654x Industrial Development Kit EVM
• AM654x Silicon Errata

Check the relevant Sitara Processors Silicon Errata document when designing a board. This document contains important information on silicon issues that affect your board design.

Other useful links:

• High-Speed Interface Layout Guidelines
• AM654x/DRA80x PCB Escape Routing Guidelines
• TI PinMux Tool

In case of any discrepancy between the TI EVMs and the device data sheet, always follow the data sheet. Despite the designer's best efforts, the EVMs may contain errors that can still function but are not completely aligned with the data sheet specification. Thus, the EVM designs should not be considered as reference designs to be blindly reused.

• Have you used the output of the power model and estimates from the rest of your design to determine the power solution needed? The power needed for each rail of the AM65x/DRA80x SoC varies based on the interfaces used and the environment in which it is operating. Power requirements must be determined using the power model.
• Have you checked that the correct voltages are applied to the correct power pins on the device? The AM65x/DRA80x SoC includes a number of power rails that must be powered with the correct voltage for proper operation.
• Have you checked that all signals connected to each of these domains are operating at the expected voltage level? The AM65x/DRA80x SoC includes twelve dual-voltage I/O domains configured for either 3.3 V or 1.8 V. All signals connected to these domains must match the voltage level provided to the associated VDDSHVx supply rail. The AM65x/DRA80x I/O buffers are not failsafe. The voltage for the VDDSHVx rail must be present before any voltage is applied to the associated I/Os.
• Have you checked that the VDDS[2:0]_WKUP and VDDS[8:0] for all rails configured for 1.8 V are connected to the 1.8-V I/O power supply? Have you checked that the VDDS[2:0]_WKUP and VDDS[8:0] for all rails configured for 3.3 V are connected to the proper internal LDO? To sequence correctly, VDDS[2:0]_WKUP and VDDS[8:0] must be supplied by either the 1.8-V I/O power supply or an internal I/O bias LDO, depending on the voltage of the rail.
• Do you have the proper capacitor value connected to each output of the internal LDOs? The AM65x/DRA80x SoC includes seventeen internal LDOs with the output of each connected to a pin on the device. The LDOs require an output capacitor connected to each of these pins.
• Does your design meet the power sequencing requirement in the data manual? Proper power supply sequencing in proper correlation with resets and clocks is required. For the recommended power sequencing requirements, see the device-specific data sheet.
• Are the filters specified in the Technical Reference manual included for the VDDA_x supply pins? AM65x/DRA80x devices contain multiple analog power pins that provide power to sensitive analog circuitry such as PLLs, DLLs, and SERDES buffers and terminations. These must be attached to filtered power sources.
• Does your design include the correct termination for your selected DDR interface type? The DDR3 and DDR4 interfaces both require a VTT termination at the end of the flyby chain for the DDR address, command and control. The VTT termination voltage is generated using a special push/pull termination regulator specifically designed to meet the VTT requirements.
• Are the DDR_VREF0 and DDR_VREF_ZQ pins left unconnected with no external voltage applied? The AM65x/DRA80x generates the DDR reference voltage internally. The DDR_VREF0 and DDR_VREF_ZQ pins are intended for observation only.
• Has the PDN analysis been performed and are the proper values and number of bypass capacitors included in your design? Use low ESL capacitors and mount them with short traces to keep the mounting inductance very low. This is required to meet the specified PDN impedance. For more details, see Sitara Processor Power Distribution Networks: Implementation and Analysis.
• Does your design include properly implemented current measurement capabilities? Zero ohm resistors in line with core and other power sections of the board are recommended for initial PCB prototype builds if you want to measure power. You should then remove the resistor in production builds and connect the power planes with wide copper or multiple vias. Power measurement is the purpose of these resistors in the EVM designs. The implementation of these resistors adds inductance and resistance that can impair power supply and power distribution performance. Current measurement on a single part should never be substituted for the values provided by the Power Model spreadsheet.

• If you are using the external MCU_PORz signal, do you have the MCU_BYP_POR pulled high? The AM65x/DRA80x component supports the internal POK circuit, which eliminates the need for a reset signal generator. If MCU_BYP_POR is pulled high, an external reset pulse with the proper timing relative to the power sequencing must be generated and connected to the MCU_PORz and PORz pins.
• If you are using the internal POK circuit, do you have the MCU_BYP_POR pulled low? If the internal POK circuit is enabled, MCU_PORz and PORz are not needed and may be pulled high. If a reset signal is needed for an external device, the MCU_PORz_OUT or PORz_OUT can be used.
• If you are using the internal POK circuit, do you have an external pull-up resistor on MCU_PORz? MCU_PORz should be pulled high if the internal POK circuit is used.
• Do you have a pull-down resistor on PORz_OUT and on MCU_PORz_OUT? The MCU_PORz_OUT and PORz_OUT signals can be used to provide the reset to other devices on the board, but they must have individual pull-down resistors. The AM65x/DRA80x does not drive the PORz_OUT and MCU_PORz_OUT until the device has started to boot. A pull-down resistor keeps the PORz_OUT and MCU_PORz_OUT signals low during the initial power sequencing.
• If you are using external MCU_PORz and PORz, do you have a reset circuit that generates the proper reset pulse? If an external reset is used, it must meet the requirements for pulse length and must be held low during power sequencing.
• Are all control pins held in the proper state until reset is released? The pins used to configure the device must be held in the desired state until after the rising edge of the MCU_PORz. If the internal POK circuit is used, they must be held in the proper state until the rising edge of MCU_PORz_OUT. MCU_PORz_OUT and PORz_OUT must have a pull-down resistor to remain in the proper state until reset is released.