TMS570LS0714

正在供货

16/32 位 RISC 闪存 MCU,Arm Cortex-R4F,通过 Q-100 车规认证

产品详情

CPU Arm Cortex-R4F Frequency (MHz) 100 Flash memory (kByte) 786 RAM (kByte) 128 ADC type 2 12-bit MibADC Total processing (MIPS) 0.0001 Features CAN, Hercules high-performance microcontroller, SPI, UART UART 1 CAN (#) 2 PWM (Ch) 29 TI functional safety category Functional Safety-Compliant Number of ADC channels 16 SPI 1 Operating temperature range (°C) -40 to 125 Rating Automotive Communication interface CAN, SPI, UART Operating system AutoSAR, FreeRTOS, SafeRTOS Hardware accelerators Floating point unit Nonvolatile memory (kByte) 786 Number of GPIOs 45 Number of I2Cs 1
CPU Arm Cortex-R4F Frequency (MHz) 100 Flash memory (kByte) 786 RAM (kByte) 128 ADC type 2 12-bit MibADC Total processing (MIPS) 0.0001 Features CAN, Hercules high-performance microcontroller, SPI, UART UART 1 CAN (#) 2 PWM (Ch) 29 TI functional safety category Functional Safety-Compliant Number of ADC channels 16 SPI 1 Operating temperature range (°C) -40 to 125 Rating Automotive Communication interface CAN, SPI, UART Operating system AutoSAR, FreeRTOS, SafeRTOS Hardware accelerators Floating point unit Nonvolatile memory (kByte) 786 Number of GPIOs 45 Number of I2Cs 1
LQFP (PZ) 100 256 mm² 16 x 16
  • High-Performance Automotive-Grade Microcontroller (MCU) for Safety-Critical Applications
    • Dual CPUs Running in Lockstep
    • ECC on Flash and RAM Interfaces
    • Built-In Self-Test (BIST) for CPU and On-chip RAMs
    • Error Signaling Module With Error Pin
    • Voltage and Clock Monitoring
  • ARM Cortex-R4F 32-Bit RISC CPU
    • 1.66 DMIPS/MHz With 8-Stage Pipeline
    • FPU With Single and Double Precision
    • 12-Region Memory Protection Unit (MPU)
    • Open Architecture With Third-Party Support
  • Operating Conditions
    • Up to 160-MHz System Clock
    • Core Supply Voltage (VCC): 1.14 to 1.32 V
    • I/O Supply Voltage (VCCIO): 3.0 to 3.6 V
  • Integrated Memory
    • 768KB of Flash With ECC
    • 128KB of RAM With ECC
    • 64KB of Flash for Emulated EEPROM With ECC
  • Common Platform Architecture
    • Consistent Memory Map Across Family
    • Real-Time Interrupt Timer (RTI) OS Timer
    • 128-Channel Vectored Interrupt Module (VIM)
    • 2-Channel Cyclic Redundancy Checker (CRC)
  • Direct Memory Access (DMA) Controller
    • 16 Channels and 32 Peripheral Requests
    • Parity for Control Packet RAM
    • DMA Accesses Protected by Dedicated MPU
  • Frequency-Modulated Phase-Locked Loop (FMPLL) With Built-In Slip Detector
  • IEEE 1149.1 JTAG, Boundary Scan and ARM CoreSight Components
  • Advanced JTAG Security Module (AJSM)
  • Up to 64 General-Purpose I/O (GIO) Pins
    • Up to 16 GIO Pins With Interrupt Generation Capability
  • Enhanced Timing Peripherals
    • 7 Enhanced Pulse Width Modulator (ePWM) Modules
    • 6 Enhanced Capture (eCAP) Modules
    • 2 Enhanced Quadrature Encoder Pulse (eQEP) Modules
  • Two Next Generation High-End Timer (N2HET) Modules
    • N2HET1: 32 Programmable Channels
    • N2HET2: 18 Programmable Channels
    • 160-Word Instruction RAM With Parity Protection Each
    • Each N2HET Includes Hardware Angle Generator
    • Dedicated High-End Timer Transfer Unit (HTU) for Each N2HET
  • Two 12-Bit Multibuffered ADC Modules
    • ADC1: 24 Channels
    • ADC2: 16 Channels
    • 16 Shared Channels
    • 64 Result Buffers With Parity Protection Each
  • Multiple Communication Interfaces
    • Up to Three CAN Controllers (DCANs)
      • 64 Mailboxes With Parity Protection Each
      • Compliant to CAN Protocol Version 2.0A and 2.0B
    • Inter-Integrated Circuit (I2C)
    • 3 Multibuffered Serial Peripheral Interfaces (MibSPIs)
      • 128 Words With Parity Protection Each
      • 8 Transfer Groups
    • One Standard Serial Peripheral Interface (SPI) Module
    • Two UART (SCI) Interfaces, One With Local Interconnect Network (LIN 2.1) Interface Support
  • Packages
    • 144-Pin Quad Flatpack (PGE) [Green]
    • 100-Pin Quad Flatpack (PZ) [Green]

All trademarks are the property of their respective owners.

  • High-Performance Automotive-Grade Microcontroller (MCU) for Safety-Critical Applications
    • Dual CPUs Running in Lockstep
    • ECC on Flash and RAM Interfaces
    • Built-In Self-Test (BIST) for CPU and On-chip RAMs
    • Error Signaling Module With Error Pin
    • Voltage and Clock Monitoring
  • ARM Cortex-R4F 32-Bit RISC CPU
    • 1.66 DMIPS/MHz With 8-Stage Pipeline
    • FPU With Single and Double Precision
    • 12-Region Memory Protection Unit (MPU)
    • Open Architecture With Third-Party Support
  • Operating Conditions
    • Up to 160-MHz System Clock
    • Core Supply Voltage (VCC): 1.14 to 1.32 V
    • I/O Supply Voltage (VCCIO): 3.0 to 3.6 V
  • Integrated Memory
    • 768KB of Flash With ECC
    • 128KB of RAM With ECC
    • 64KB of Flash for Emulated EEPROM With ECC
  • Common Platform Architecture
    • Consistent Memory Map Across Family
    • Real-Time Interrupt Timer (RTI) OS Timer
    • 128-Channel Vectored Interrupt Module (VIM)
    • 2-Channel Cyclic Redundancy Checker (CRC)
  • Direct Memory Access (DMA) Controller
    • 16 Channels and 32 Peripheral Requests
    • Parity for Control Packet RAM
    • DMA Accesses Protected by Dedicated MPU
  • Frequency-Modulated Phase-Locked Loop (FMPLL) With Built-In Slip Detector
  • IEEE 1149.1 JTAG, Boundary Scan and ARM CoreSight Components
  • Advanced JTAG Security Module (AJSM)
  • Up to 64 General-Purpose I/O (GIO) Pins
    • Up to 16 GIO Pins With Interrupt Generation Capability
  • Enhanced Timing Peripherals
    • 7 Enhanced Pulse Width Modulator (ePWM) Modules
    • 6 Enhanced Capture (eCAP) Modules
    • 2 Enhanced Quadrature Encoder Pulse (eQEP) Modules
  • Two Next Generation High-End Timer (N2HET) Modules
    • N2HET1: 32 Programmable Channels
    • N2HET2: 18 Programmable Channels
    • 160-Word Instruction RAM With Parity Protection Each
    • Each N2HET Includes Hardware Angle Generator
    • Dedicated High-End Timer Transfer Unit (HTU) for Each N2HET
  • Two 12-Bit Multibuffered ADC Modules
    • ADC1: 24 Channels
    • ADC2: 16 Channels
    • 16 Shared Channels
    • 64 Result Buffers With Parity Protection Each
  • Multiple Communication Interfaces
    • Up to Three CAN Controllers (DCANs)
      • 64 Mailboxes With Parity Protection Each
      • Compliant to CAN Protocol Version 2.0A and 2.0B
    • Inter-Integrated Circuit (I2C)
    • 3 Multibuffered Serial Peripheral Interfaces (MibSPIs)
      • 128 Words With Parity Protection Each
      • 8 Transfer Groups
    • One Standard Serial Peripheral Interface (SPI) Module
    • Two UART (SCI) Interfaces, One With Local Interconnect Network (LIN 2.1) Interface Support
  • Packages
    • 144-Pin Quad Flatpack (PGE) [Green]
    • 100-Pin Quad Flatpack (PZ) [Green]

All trademarks are the property of their respective owners.

The TMS570LS0714 device is part of the Hercules TMS570 series of high-performance automotive-grade ARM® Cortex®-R-based MCUs. Comprehensive documentation, tools, and software are available to assist in the development of ISO 26262 and IEC 61508 functional safety applications. Start evaluating today with the Hercules Hercules TMS570 LaunchPad Development Kit. The TMS570LS0714 device has on-chip diagnostic features including: dual CPUs in lockstep; CPU and memory Built-In Self-Test (BIST) logic; ECC on both the flash and the SRAM; parity on peripheral memories; and loopback capability on most peripheral I/Os.

The TMS570LS0714 device integrates the ARM Cortex-R4F floating-point CPU which offers an efficient 1.66 DMIPS/MHz, and has configurations which can run up to 160 MHz providing up to 265 DMIPS. The TMS570 device supports the word invariant big-endian [BE32] format.

The TMS570LS0714 device has 768KB of integrated flash and 128KB of RAM configurations with single-bit error correction and double-bit error detection. The flash memory on this device is nonvolatile, electrically erasable and programmable, and is implemented with a 64-bit-wide data bus interface. The flash operates on a 3.3-V supply input (same level as the I/O supply) for all read, program, and erase operations. The SRAM supports single-cycle read and write accesses in byte, halfword, word, and doubleword modes throughout the supported frequency range.

The TMS570LS0714 device features peripherals for real-time control-based applications, including two Next-Generation High-End Timer (N2HET) timing coprocessors with up to 44 total I/O terminals, seven Enhanced PWM (ePWM) modules with up to 14 outputs, six Enhanced Capture (eCAP) modules, two Enhanced Quadrature Encoder Pulse (eQEP) modules, and two 12-bit Analog-to-Digital Converters (ADCs) supporting up to 24 inputs.

The N2HET is an advanced intelligent timer that provides sophisticated timing functions for real-time applications. The timer is software-controlled, using a reduced instruction set, with a specialized timer micromachine and an attached I/O port. The N2HET can be used for pulse-width-modulated outputs, capture or compare inputs, or general-purpose I/O (GIO). The N2HET is especially well suited for applications requiring multiple sensor information and drive actuators with complex and accurate time pulses. A High-End Timer Transfer Unit (HTU) can transfer N2HET data to or from main memory. A Memory Protection Unit (MPU) is built into the HTU.

The ePWM module can generate complex pulse width waveforms with minimal CPU overhead or intervention. The ePWM is easy to use and supports complementary PWMs and deadband generation. With integrated trip zone protection and synchronization with the on-chip MibADC, the ePWM is ideal for digital motor control applications.

The eCAP module is essential in systems where the accurately timed capture of external events is important. The eCAP can also be used to monitor the ePWM outputs or to generate simple PWM when not needed for capture applications.

The eQEP module is used for direct interface with a linear or rotary incremental encoder to get position, direction, and speed information from a rotating machine as used in high-performance motion and position-control systems.

The device has two 12-bit-resolution MibADCs with 24 total inputs and 64 words of parity-protected buffer RAM each. The MibADC channels can be converted individually or can be grouped by software for sequential conversion sequences. Sixteen inputs are shared between the two MibADCs. There are three separate groups. Each group can be converted once when triggered or configured for continuous conversion mode. The MibADC has a 10-bit mode for use when compatibility with older devices or faster conversion time is desired.

The device has multiple communication interfaces: three MibSPIs; two SPIs; two SCIs, one of which can be used as LIN; up to three DCANs; and one I2C module. The SPI provides a convenient method of serial interaction for high-speed communications between similar shift-register type devices. The LIN supports the Local Interconnect standard 2.0 and can be used as a UART in full-duplex mode using the standard Non-Return-to-Zero (NRZ) format. The DCAN supports the CAN 2.0B protocol standard and uses a serial, multimaster communication protocol that efficiently supports distributed real-time control with robust communication rates of up to 1 Mbps. The DCAN is ideal for applications operating in noisy and harsh environments (for example, automotive and industrial fields) that require reliable serial communication or multiplexed wiring.

The I2C module is a multimaster communication module providing an interface between the microcontroller and an I2C-compatible device through the I2C serial bus. The I2C module supports speeds of 100 and 400 kbps.

A Frequency-Modulated Phase-Locked Loop (FMPLL) clock module is used to multiply the external frequency reference to a higher frequency for internal use. The FMPLL provides one of the six possible clock source inputs to the Global Clock Module (GCM). The GCM manages the mapping between the available clock sources and the device clock domains.

The device also has an external clock prescaler (ECP) circuit that when enabled, outputs a continuous external clock on the ECLK terminal. The ECLK frequency is a user-programmable ratio of the peripheral interface clock (VCLK) frequency. This low-frequency output can be monitored externally as an indicator of the device operating frequency.

The Direct Memory Access (DMA) controller has 16 channels, 32 peripheral requests, and parity protection on its memory. An MPU is built into the DMA to protect memory against erroneous transfers.

The Error Signaling Module (ESM) monitors device errors and determines whether an interrupt or external error signal (nERROR) is asserted when a fault is detected. The nERROR terminal can be monitored externally as an indicator of a fault condition in the microcontroller.

With integrated functional safety features and a wide choice of communication and control peripherals, the TMS570LS0714 device is an ideal solution for high-performance, real-time control applications with safety-critical

The TMS570LS0714 device is part of the Hercules TMS570 series of high-performance automotive-grade ARM® Cortex®-R-based MCUs. Comprehensive documentation, tools, and software are available to assist in the development of ISO 26262 and IEC 61508 functional safety applications. Start evaluating today with the Hercules Hercules TMS570 LaunchPad Development Kit. The TMS570LS0714 device has on-chip diagnostic features including: dual CPUs in lockstep; CPU and memory Built-In Self-Test (BIST) logic; ECC on both the flash and the SRAM; parity on peripheral memories; and loopback capability on most peripheral I/Os.

The TMS570LS0714 device integrates the ARM Cortex-R4F floating-point CPU which offers an efficient 1.66 DMIPS/MHz, and has configurations which can run up to 160 MHz providing up to 265 DMIPS. The TMS570 device supports the word invariant big-endian [BE32] format.

The TMS570LS0714 device has 768KB of integrated flash and 128KB of RAM configurations with single-bit error correction and double-bit error detection. The flash memory on this device is nonvolatile, electrically erasable and programmable, and is implemented with a 64-bit-wide data bus interface. The flash operates on a 3.3-V supply input (same level as the I/O supply) for all read, program, and erase operations. The SRAM supports single-cycle read and write accesses in byte, halfword, word, and doubleword modes throughout the supported frequency range.

The TMS570LS0714 device features peripherals for real-time control-based applications, including two Next-Generation High-End Timer (N2HET) timing coprocessors with up to 44 total I/O terminals, seven Enhanced PWM (ePWM) modules with up to 14 outputs, six Enhanced Capture (eCAP) modules, two Enhanced Quadrature Encoder Pulse (eQEP) modules, and two 12-bit Analog-to-Digital Converters (ADCs) supporting up to 24 inputs.

The N2HET is an advanced intelligent timer that provides sophisticated timing functions for real-time applications. The timer is software-controlled, using a reduced instruction set, with a specialized timer micromachine and an attached I/O port. The N2HET can be used for pulse-width-modulated outputs, capture or compare inputs, or general-purpose I/O (GIO). The N2HET is especially well suited for applications requiring multiple sensor information and drive actuators with complex and accurate time pulses. A High-End Timer Transfer Unit (HTU) can transfer N2HET data to or from main memory. A Memory Protection Unit (MPU) is built into the HTU.

The ePWM module can generate complex pulse width waveforms with minimal CPU overhead or intervention. The ePWM is easy to use and supports complementary PWMs and deadband generation. With integrated trip zone protection and synchronization with the on-chip MibADC, the ePWM is ideal for digital motor control applications.

The eCAP module is essential in systems where the accurately timed capture of external events is important. The eCAP can also be used to monitor the ePWM outputs or to generate simple PWM when not needed for capture applications.

The eQEP module is used for direct interface with a linear or rotary incremental encoder to get position, direction, and speed information from a rotating machine as used in high-performance motion and position-control systems.

The device has two 12-bit-resolution MibADCs with 24 total inputs and 64 words of parity-protected buffer RAM each. The MibADC channels can be converted individually or can be grouped by software for sequential conversion sequences. Sixteen inputs are shared between the two MibADCs. There are three separate groups. Each group can be converted once when triggered or configured for continuous conversion mode. The MibADC has a 10-bit mode for use when compatibility with older devices or faster conversion time is desired.

The device has multiple communication interfaces: three MibSPIs; two SPIs; two SCIs, one of which can be used as LIN; up to three DCANs; and one I2C module. The SPI provides a convenient method of serial interaction for high-speed communications between similar shift-register type devices. The LIN supports the Local Interconnect standard 2.0 and can be used as a UART in full-duplex mode using the standard Non-Return-to-Zero (NRZ) format. The DCAN supports the CAN 2.0B protocol standard and uses a serial, multimaster communication protocol that efficiently supports distributed real-time control with robust communication rates of up to 1 Mbps. The DCAN is ideal for applications operating in noisy and harsh environments (for example, automotive and industrial fields) that require reliable serial communication or multiplexed wiring.

The I2C module is a multimaster communication module providing an interface between the microcontroller and an I2C-compatible device through the I2C serial bus. The I2C module supports speeds of 100 and 400 kbps.

A Frequency-Modulated Phase-Locked Loop (FMPLL) clock module is used to multiply the external frequency reference to a higher frequency for internal use. The FMPLL provides one of the six possible clock source inputs to the Global Clock Module (GCM). The GCM manages the mapping between the available clock sources and the device clock domains.

The device also has an external clock prescaler (ECP) circuit that when enabled, outputs a continuous external clock on the ECLK terminal. The ECLK frequency is a user-programmable ratio of the peripheral interface clock (VCLK) frequency. This low-frequency output can be monitored externally as an indicator of the device operating frequency.

The Direct Memory Access (DMA) controller has 16 channels, 32 peripheral requests, and parity protection on its memory. An MPU is built into the DMA to protect memory against erroneous transfers.

The Error Signaling Module (ESM) monitors device errors and determines whether an interrupt or external error signal (nERROR) is asserted when a fault is detected. The nERROR terminal can be monitored externally as an indicator of a fault condition in the microcontroller.

With integrated functional safety features and a wide choice of communication and control peripherals, the TMS570LS0714 device is an ideal solution for high-performance, real-time control applications with safety-critical

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Hercules TMS570LS0714 经 TÜV SÜD 认证,能够满足 ISO 26262 ASIL D 和 IEC 61508 SIL 3 标准,有助于简化功能安全应用的开发。立即下载证书。

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类型 标题 下载最新的英语版本 日期
* 数据表 TMS570LS0714 16- and 32-Bit RISC Flash Microcontroller 数据表 (Rev. E) PDF | HTML 2016年 11月 10日
* 勘误表 TMS570LS09/07xx Microcontroller Silicon Errata (Silicon Rev 0) (Rev. D) 2016年 5月 31日
* 勘误表 TMS570LS09/07xx Microcontroller Silicon Errata (Silicon Rev A) (Rev. B) 2016年 5月 31日
* 用户指南 TMS570LS09x/07x 16/32-Bit RISC Flash Microcontroller Technical Reference Manual (Rev. A) 2018年 3月 1日
功能安全信息 Certification for Functional Safety Hardware Process (Rev. C) 2025年 6月 6日
证书 TUEV SUED Certificate for TMS570LS09X/07x (Rev. B) 2024年 6月 21日
更多文献资料 Hercules™ Diagnostic Library Test Automation Unit User Guide (Rev. B) PDF | HTML 2020年 1月 9日
更多文献资料 HALCoGen-CSP 04.07.01 (Rev. C) PDF | HTML 2020年 1月 8日
功能安全信息 HALCoGen-CSP Installation Guide (Rev. B) PDF | HTML 2020年 1月 8日
功能安全信息 HALCoGen-CSP User's Guide (Rev. C) PDF | HTML 2020年 1月 8日
功能安全信息 Hercules Diagnostic Library -TAU Installation Guide (Rev. B) PDF | HTML 2020年 1月 8日
用户指南 Hercules Diagnostic Library CSP Without LDRA 2019年 10月 29日
更多文献资料 Diagnostic Library CSP Release Notes 2019年 10月 17日
功能安全信息 SafeTI™ Hercules™ Diagnostic Library Release Notes (Rev. A) 2019年 9月 24日
应用手册 Hercules PLL Advisory SSWF021#45 Workaround (Rev. B) PDF | HTML 2019年 9月 9日
应用手册 CAN Bus Bootloader for Hercules Microcontrollers PDF | HTML 2019年 8月 21日
应用手册 HALCoGen CSP Without LDRA Release_Notes 2019年 8月 19日
用户指南 HALCoGen-CSP Without LDRA Installation Guide PDF | HTML 2019年 8月 19日
用户指南 HALCoGen-CSP Without LDRA User's Guide PDF | HTML 2019年 8月 19日
用户指南 Hercules Diagnostic Library - Without LDRA Installation Guide PDF | HTML 2019年 8月 19日
用户指南 Hercules™ Diag Lib Test Automation Unit Without LDRA User's Guide PDF | HTML 2019年 8月 19日
应用手册 Interfacing the Embedded 12-Bit ADC in a TMS570LS31x/21x and RM4x Series MCUs (Rev. A) 2018年 4月 20日
应用手册 FreeRTOS on Hercules Devices_new 2018年 4月 19日
应用手册 Sharing FEE Blocks Between the Bootloader and the Application 2017年 11月 7日
用户指南 Hercules™ TMS570LS12x/RM46 LaunchPad User's Guide 2017年 5月 31日
应用手册 Sharing Exception Vectors on Hercules™ Based Microcontrollers 2017年 3月 27日
功能安全信息 Safety Manual for TMS570LS07x/09x Hercules ARM Safety Critical MCUs (Rev. A) 2016年 12月 12日
应用手册 Hercules AJSM Unlock (Rev. A) PDF | HTML 2016年 10月 19日
应用手册 How to Create a HALCoGen Based Project For CCS (Rev. B) 2016年 8月 9日
应用手册 Using the CRC Module on Hercules™-Based Microcontrollers 2016年 8月 4日
应用手册 Migrating from TMS570LS12x/11x to TMS570LS09x/07x MCUs (Rev. A) 2016年 6月 15日
功能安全信息 Functional Safety Audit: SafeTI Functional Safety Hardware Development (Rev. A) 2016年 4月 25日
应用手册 High Speed Serial Bus Using the MibSPIP Module on Hercules-Based MCUs 2016年 4月 22日
功能安全信息 Enabling Functional Safety Using SafeTI Diagnostic Library 2015年 12月 18日
功能安全信息 Safety Manual for TMS570LS12x/11x Hercules ARM Safety Critical MCUs (Rev. B) 2015年 12月 11日
应用手册 Triggering ADC Using Internal Timer Events on Hercules MCUs 2015年 10月 19日
白皮书 Extending TI’s Hercules MCUs with the integrated flexible HET 2015年 9月 29日
应用手册 Continuous Monitor of the PLL Frequency With the DCC 2015年 7月 24日
应用手册 PWM Generation and Input Capture Using HALCoGen N2HET Module 2015年 6月 30日
功能安全信息 Foundational Software for Functional Safety 2015年 5月 12日
应用手册 Sine Wave Generation Using PWM With Hercules N2HET and HTU 2015年 5月 12日
应用手册 Triangle/Trapezoid Wave Generation Using PWM With Hercules N2HET 2015年 5月 1日
应用手册 Nested Interrupts on Hercules ARM Cortex-R4/5-Based Microncontrollers 2015年 4月 23日
白皮书 Latch-Up White Paper PDF | HTML 2015年 4月 22日
应用手册 Interrupt and Exception Handling on Hercules ARM Cortex-R4/5-Based MCUs 2015年 4月 20日
应用手册 Monitoring PWM Using N2HET 2015年 4月 2日
应用手册 Hercules SCI With DMA 2015年 3月 22日
证书 TÜV NORD Certificate for Functional Safety Software Development Process 2015年 2月 3日
功能安全信息 Calculating Equivalent Power-on-Hours for Hercules Safety MCUs 2015年 1月 26日
应用手册 Limiting Clamp Currents on TMS470/TMS570 Digital and Analog Inputs (Rev. A) 2014年 12月 8日
功能安全信息 TUV SUD ISO-13849 Safety Architecture Concept Study 2014年 7月 2日
更多文献资料 HaLCoGen Release Notes 2014年 6月 25日
应用手册 Interfacing TPS65381 With Hercules Microcontrollers (Rev. A) 2014年 2月 14日
用户指南 TMS570LS12x Hercules Development Kit (HDK) User's Guide (Rev. A) 2013年 10月 10日
功能安全信息 IEC 60730 and UL 1998 Safety Standard Compliance Made Easier with TI Hercules 2013年 10月 3日
应用手册 CAN Bus Bootloader for TMS570LS12X MCU 2013年 9月 16日
应用手册 SPI Bootloader for Hercules TMS570LS12X MCU 2013年 9月 16日
应用手册 UART Bootloader for Hercules TMS570LS12X MCU 2013年 9月 16日
白皮书 Model-Based Tool Qualification of the TI C/C++ ARM® Compiler 2013年 6月 6日
功能安全信息 Accelerating safety-certified motor control designs (Rev. A) 2012年 10月 4日
应用手册 Hercules Family Frequency Slewing to Reduce Voltage and Current Transients 2012年 7月 5日
应用手册 Basic PBIST Configuration and Influence on Current Consumption (Rev. C) 2012年 4月 12日
应用手册 Verification of Data Integrity Using CRC 2012年 2月 17日
用户指南 HET Integrated Development Environment User's Guide (Rev. A) 2011年 11月 17日
功能安全信息 Important ARM Ltd Application Notes for TI Hercules ARM Safety MCUs 2011年 11月 17日
功能安全信息 Execution Time Measurement for Hercules ARM Safety MCUs (Rev. A) 2011年 11月 4日
应用手册 Use of All 1'’s and All 0's Valid in Flash EEPROM Emulation 2011年 9月 27日
应用手册 3.3 V I/O Considerations for Hercules Safety MCUs (Rev. A) 2011年 9月 6日
功能安全信息 Configuring the Hercules ARM Safety MCU SCI/LIN Module for UART Communication (Rev. A) 2011年 9月 6日
功能安全信息 Hercules™ Microcontrollers: Real-time MCUs for safety-critical products 2011年 9月 2日
应用手册 ECC Handling in TMSx70-Based Microcontrollers 2011年 2月 23日
用户指南 TI ICEPick Module Type C Reference Guide Public Version 2011年 2月 17日
应用手册 NHET Getting Started (Rev. B) 2010年 8月 30日
功能安全信息 Generating Operating System Tick Using RTI on a Hercules ARM Safety MCU 2010年 7月 13日
功能安全信息 Usage of MPU Subregions on TI Hercules ARM Safety MCUs 2010年 3月 10日
用户指南 TI Assembly Language Tools Enhanced High-End Timer (NHET) Assembler User's Guide 2010年 3月 4日
白皮书 Discriminating between Soft Errors and Hard Errors in RAM White Paper 2008年 6月 4日

订购和质量

包含信息:
  • RoHS
  • REACH
  • 器件标识
  • 引脚镀层/焊球材料
  • MSL 等级/回流焊峰值温度
  • MTBF/时基故障估算
  • 材料成分
  • 鉴定摘要
  • 持续可靠性监测
包含信息:
  • 制造厂地点
  • 封装厂地点

支持和培训

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