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數據轉換器
類比轉數位轉換器 (ADC)
高速 ADC (≥10 MSPS)

ADS61JB23

現行

12 位元 80-MSPS 類比轉數位轉換器 (ADC)

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產品規格表

ADS61JB23

現行
產品規格表 立即訂購

產品詳細資料

Sample rate (max) (Msps) 80 Resolution (Bits) 12 Number of input channels 1 Interface type JESD204A Analog input BW (MHz) 480 Features High Performance Rating Catalog Peak-to-peak input voltage range (V) 2 Power consumption (typ) (mW) 440 Architecture Pipeline SNR (dB) 71.7 ENOB (Bits) 11.5 SFDR (dB) 80 Operating temperature range (°C) -40 to 85 Input buffer Yes
Sample rate (max) (Msps) 80 Resolution (Bits) 12 Number of input channels 1 Interface type JESD204A Analog input BW (MHz) 480 Features High Performance Rating Catalog Peak-to-peak input voltage range (V) 2 Power consumption (typ) (mW) 440 Architecture Pipeline SNR (dB) 71.7 ENOB (Bits) 11.5 SFDR (dB) 80 Operating temperature range (°C) -40 to 85 Input buffer Yes
VQFN (RHA) 40 36 mm² 6 x 6
  • Output Interface:
    • Single-Lane and Dual-Lane Interfaces
    • Maximum Data Rate of 1.6 Gbps
    • Meets JESD204A Specification
    • CML Outputs with Current Programmable from 2 mA – 32 mA
  • Power Dissipation:
    • 440 mW at 80 MSPS in Single Lane Mode
    • Power Scales Down with Clock Rate
  • Input Interface: Buffered Analog Inputs
  • 71.7 dBFS SNR at 70 MHz IF
  • Analog Input FSR: 2 Vpp
  • External and Internal (trimmed) Reference Support
  • 1.8V Supply (Analog and digital), 3.3 V Supply for Input Buffer
  • Programmable Digital Gain: 0dB – 6dB
  • Straight Offset Binary or Twos Complement Output
  • Package:
    • 6 mm × 6 mm QFN-40
  • Output Interface:
    • Single-Lane and Dual-Lane Interfaces
    • Maximum Data Rate of 1.6 Gbps
    • Meets JESD204A Specification
    • CML Outputs with Current Programmable from 2 mA – 32 mA
  • Power Dissipation:
    • 440 mW at 80 MSPS in Single Lane Mode
    • Power Scales Down with Clock Rate
  • Input Interface: Buffered Analog Inputs
  • 71.7 dBFS SNR at 70 MHz IF
  • Analog Input FSR: 2 Vpp
  • External and Internal (trimmed) Reference Support
  • 1.8V Supply (Analog and digital), 3.3 V Supply for Input Buffer
  • Programmable Digital Gain: 0dB – 6dB
  • Straight Offset Binary or Twos Complement Output
  • Package:
    • 6 mm × 6 mm QFN-40

The ADS61JB23 is a high-performance, low-power, single channel analog-to-digital converter with an integrated JESD204A output interface. Available in a 6 mm × 6 mm QFN package, with both single-lane and dual-lane output modes, the ADS61JB23 offers an unprecedented level of compactness. The output interface is compatible to the JESD204A standard, with an additional mode (as per IEEE Std 802.3-2002 part3, Clause 36.2.4.12) to interface seamlessly to the TI TLK family of SERDES transceivers. Equally impressive is the inclusion of an on-chip analog input buffer, providing isolation between the sample/hold switches and higher and more consistent input impedance.

The ADS61JB23 is specified over the industrial temperature range (–40°C to 85°C).

The ADS61JB23 is a high-performance, low-power, single channel analog-to-digital converter with an integrated JESD204A output interface. Available in a 6 mm × 6 mm QFN package, with both single-lane and dual-lane output modes, the ADS61JB23 offers an unprecedented level of compactness. The output interface is compatible to the JESD204A standard, with an additional mode (as per IEEE Std 802.3-2002 part3, Clause 36.2.4.12) to interface seamlessly to the TI TLK family of SERDES transceivers. Equally impressive is the inclusion of an on-chip analog input buffer, providing isolation between the sample/hold switches and higher and more consistent input impedance.

The ADS61JB23 is specified over the industrial temperature range (–40°C to 85°C).
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重要文件 類型 標題 格式選項 日期
* Data sheet 12-Bit Input-Buffered 80 MSPS ADC with JESD204A Output Interface datasheet 2012年 12月 1日
Application note Design Considerations for Avoiding Timing Errors during High-Speed ADC, LVDS Dat (Rev. A) 2015年 5月 22日
Application note Why Use Oversampling when Undersampling Can Do the Job? (Rev. A) 2013年 7月 19日

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韌體

TI204C-IP — Request for JESD204 rapid design IP

The JESD204 rapid design IP has been designed to enable FPGA engineers to achieve an accelerated path to a working JESD204 system. The IP has been architected in a way that downstream digital processing and other application logic are isolated from most of the performance- and timing-critical (...)

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開發模組 (EVM) 的 GUI

DATACONVERTERPRO-SW — High Speed Data Converter Pro GUI Installer, v5.31

This high-speed data converter pro GUI is a PC (Windows® XP/7/10 compatible) program designed to aid in evaluation of most TI high-speed data converter [analog-to-digital converter (ADC) and digital-to-analog converter (DAC)] and analog front-end (AFE) platforms. Designed to support the entire (...)

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開發模組 (EVM) 的 GUI

SLAC530 — ADS61JB23 SPI GUI Installer

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支援軟體

SBAC120 — TIGAR Support Files

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模擬型號

ADS61JBXX IBIS Model

SLOM341.ZIP (110 KB) - IBIS Model
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計算工具

ANALOG-ENGINEER-CALC — PC software analog engineer's calculator

The analog engineer’s calculator is designed to speed up many of the repetitive calculations that analog circuit design engineers use on a regular basis. This PC-based tool provides a graphical interface with a list of various common calculations ranging from setting operational-amplifier (...)

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設計工具

SBAC119 — TIGAR (Texas Instruments Graphical Evaluation of ADC Response Tool)

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模擬工具

PSPICE-FOR-TI — PSpice® for TI 設計與模擬工具

PSpice® for TI 是有助於評估類比電路功能的設計和模擬環境。這款全功能設計和模擬套件使用 Cadence® 的類比分析引擎。PSpice for TI 包括業界最大的模型庫之一，涵蓋我們的類比和電源產品組合，以及特定類比行為模型，且使用無需支付費用。

PSpice for TI 設計和模擬環境可讓您使用其內建函式庫來模擬複雜的混合訊號設計。在進行佈局和製造之前，建立完整的終端設備設計和解決方案原型，進而縮短上市時間並降低開發成本。 

在 PSpice for TI 設計與模擬工具中，您可以搜尋 TI (...)
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VQFN (RHA) 40 Ultra Librarian
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