ADS62C17
- Maximum Sample Rate: 200 MSPS
- 11-bit Resolution with No Missing Codes
- 90 dBc SFDR at Fin = 10 MHz
- 79.8 dBFS SNR at 125 MHz IF, 20 MHz BW
using TI proprietary SNRBoost technology - Total Power 1.1 W at 200 MSPS
- 90 dB Cross-talk
- Double Data Rate (DDR) LVDS and Parallel
CMOS Output Options - Programmable Gain up to 6dB for SNR/SFDR Trade-off
- DC Offset Correction
- Gain Tuning Capability in Fine Steps (0.001 dB)
Allows Channel-to-channel Gain Matching - Supports Input Clock Amplitude Down to
400 mV p-p Differential - Internal and External Reference Support
- 64-QFN Package (9 mm × 9 mm)
ADS62C17 is a dual channel 11-bit, 200 MSPS A/D converter that combines high dynamic performance and low power consumption in a compact 64 QFN package. This makes it well-suited for multi-carrier, wide band-width communications applications.
ADS62C17 uses TI-proprietary SNRBoost technology that can be used to overcome SNR limitation due to quantization noise for bandwidths less than Nyquist (Fs/2). It includes several useful and commonly used digital functions such as ADC offset correction, gain (0 to 6 dB in steps of 0.5 dB) and gain tuning (in fine steps of 0.001 dB).
The gain option can be used to improve SFDR performance at lower full-scale input ranges. Using the gain tuning capability, each channel’s gain can be set independently to improve channel-to-channel gain matching. The device also includes a dc offset correction loop that can be used to cancel the ADC offset.
Both DDR LVDS (Double Data Rate) and parallel CMOS digital output interfaces are available. It includes internal references while the traditional reference pins and associated decoupling capacitors have been eliminated. Nevertheless, the device can also be driven with an external reference.
The device is specified over the industrial temperature range (–40°C to 85°C).
技術文件
| 重要文件 | 類型 | 標題 | 格式選項 | 下載最新的英文版本 | 日期 | |
|---|---|---|---|---|---|---|
| * | 資料表 | Dual Channel 11 Bit, 200 MSPS ADC with SNRBoost datasheet (Rev. A) | 2009/7/17 | |||
| 應用說明 | Design Considerations for Avoiding Timing Errors during High-Speed ADC, LVDS Dat (Rev. A) | 2015/5/22 | ||||
| 應用說明 | Why Use Oversampling when Undersampling Can Do the Job? (Rev. A) | 2013/7/19 | ||||
| 使用指南 | TSW4200 Demonstration Kit User's Guide (Rev. C) | 2012/10/31 | ||||
| 應用說明 | Understanding Low-Amplitude Behavior of 11-bit ADCs | 2011/10/22 | ||||
| 應用說明 | Driving High-Speed ADCs: Circuit Topologies and System-Level Parameters (Rev. A) | 2010/9/10 | ||||
| 應用說明 | Smart Selection of ADC/DAC Enables Better Design of Software-Defined Radio | 2009/4/28 | ||||
| 應用說明 | CDCE62005 as Clock Solution for High-Speed ADCs | 2008/9/4 | ||||
| 應用說明 | CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital Converters | 2008/6/8 | ||||
| 應用說明 | Phase Noise Performance and Jitter Cleaning Ability of CDCE72010 | 2008/6/2 | ||||
| 應用說明 | QFN Layout Guidelines | 2006/7/28 |
設計與開發
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| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| VQFN (RGC) | 64 | Ultra Librarian |