The ADS58J64 is a low-power, wide-bandwidth, 14-bit, 1-GSPS, quad-channel, telecom receiver device. The ADS58J64 supports a JESD204B serial interface with data rates up to 10 Gbps with one lane per channel. The buffered analog input provides uniform input impedance across a wide frequency range and minimizes sample-and-hold glitch energy. The ADS58J64 provides excellent spurious-free dynamic range (SFDR) over a large input frequency range with very low power consumption. The digital signal processing block includes complex mixers followed by low-pass filters with decimate-by-2 and -4 options supporting up to a 200-MHz receive bandwidth. The ADS58J64 also supports a 14-bit, 500-MSPS output in burst mode, making the device suitable for a digital pre-distortion (DPD) observation receiver.
The JESD204B interface reduces the number of interface lines, thus allowing high system integration density. An internal phase-locked loop (PLL) multiplies the incoming analog-to-digital converter (ADC) sampling clock to derive the bit clock that is used to serialize the 14-bit data from each channel.
| 重要文件 | 類型 | 標題 | 格式選項 | 日期 |
|---|---|---|---|---|
| * | Data sheet | ADS58J64 Quad-Channel, 14-Bit, 1-GSPS Telecom Receiver Device datasheet (Rev. B) | PDF | HTML | 2021年 12月 21日 |
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ADS58J64EVM 是用於評估德州儀器 ADS58J64 整合式接收器的評估板。ADS58J64 是一款具有緩衝類比輸入的低功率、14 位元、500-MSPS、四通道電信接收器。裝置支援 JESD204B 介面和高達 10Gbps 的資料速率。EVM 具有變壓器耦合類比和時鐘輸入，可支援單端訊號和時鐘來源，並適應廣泛的訊號頻率。類比輸入的變壓器背對背連接，以獲得更佳的振幅和相位比對性能。板載時鐘合成器/配電晶片 LMK04828 可用於為 ADC 和資料擷取板 (TSW14J56EVM) 的 JESD204B 介面提供超低抖動和相位雜訊裝置時鐘，以及比對的系統參考時鐘 (...)
The JESD204 rapid design IP has been designed to enable FPGA engineers to achieve an accelerated path to a working JESD204 system. The IP has been architected in a way that downstream digital processing and other application logic are isolated from most of the performance- and timing-critical (...)
This high-speed data converter pro GUI is a PC (Windows® XP/7/10 compatible) program designed to aid in evaluation of most TI high-speed data converter [analog-to-digital converter (ADC) and digital-to-analog converter (DAC)] and analog front-end (AFE) platforms. Designed to support the entire (...)
The analog engineer’s calculator is designed to speed up many of the repetitive calculations that analog circuit design engineers use on a regular basis. This PC-based tool provides a graphical interface with a list of various common calculations ranging from setting operational-amplifier (...)
| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| VQFN (RRH) | 72 | Ultra Librarian |
| VQFNP (RMP) | 72 | Ultra Librarian |
建議產品可能具有與此 TI 產品相關的參數、評估模組或參考設計。
Analog Engineer's Calc Installer
General calculator tool for analog design support.
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