ADS125H18
- Programmable data rate up to 1.067MSPS
- High impedance voltage divider with integrated precision matched resistors
- Analog multiplexer with 17 independently selectable inputs:
- Up to 8 fully differential inputs
- Up to 16 single ended inputs
- Rail-to-rail analog input buffer and reference buffer
- Internal voltage reference, selectable output 2.5V or 4.096V
- Fault detection and monitor circuits
- General-Purpose I/Os
- Internal Oscillator: 25.6MHz, 1% Accuracy
- Channel auto-sequencer and FIFO buffer
- Simultaneous 50Hz and 60Hz rejection at ≤ 25 SPS with low-latency digital filter
- Power-scalable architecture with four speed modes
The ADS125H18 is a high voltage input, multiplexed 8/16-Channel, 24 bit, delta-sigma (ΔΣ), analog-to-digital converter (ADC) with data rates up to 1MSPS and is configurable to accept up to 8 fully differential analog inputs or up to 16 single-ended analog inputs. Each input comprises a high-impedance voltage divider with integrated precision matched resistors to scale down the input voltage to the input range of the ADC. The device offers an excellent combination of ac performance and dc precision with low power consumption.
The ADS125H18 is equipped with a channel auto-sequencer and a FIFO (first-in, first-out) buffer. The power-scalable architecture provides four speed modes to optimize data rate, resolution, and power consumption.
The small 5mm × 5mm VQFN package is designed for limited space applications. The device is fully specified for operation over the –40°C to +125°C temperature range.
技術文件
| 重要文件 | 類型 | 標題 | 格式選項 | 日期 |
|---|---|---|---|---|
| * | Data sheet | ADS125H18 8/16-Channel, 1MSPS , 24 -Bit, Delta-Sigma ADC datasheet | PDF | HTML | 2025年 12月 16日 |
| Circuit design | 來自 +5V 供電電源且用於高電壓資料轉換器的精密、±15V 電 源供應電路 | PDF | HTML | 2025年 12月 9日 | |
| Circuit design | 4-Ch, diff. in., DAQ front-end circuit w/ configurable voltage & current inputs (Rev. A) | PDF | HTML | 2024年 9月 19日 | |
| Application note | Calculating Conversion Latency and System Cycle Time for Delta-Sigma ADCs (Rev. A) | PDF | HTML | 2024年 3月 18日 | |
| Application note | Digital Filter Types in Delta-Sigma ADCs (Rev. A) | PDF | HTML | 2023年 3月 29日 | |
| Product overview | PLC Analog Input Front-End Architectures | PDF | HTML | 2022年 7月 31日 | |
| E-book | Fundamentals of Precision ADC Noise Analysis (Rev. A) | 2020年 6月 19日 |
設計與開發
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ADS125H18EVM-PDK — ADS125H18 評估模組
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| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| VQFN (RHB) | 36 | Ultra Librarian |
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