ADS62P15
- Maximum Sample Rate: 125 MSPS
- 11-Bit Resolution With No Missing Codes
- 84 dBc SFDR at Fin = 50 MHz
- 67.1 dBFS SNR at Fin = 50 MHz
- 92 dB Crosstalk
- Parallel CMOS and DDR LVDS Output Options
- 3.5 dB Coarse Gain and Programmable Fine Gain
up to 6 dB for SNR/SFDR Trade-Off - Digital Processing Block With:
- Offset Correction
- Fine Gain Correction, in Steps of 0.05 dB
- Decimation by 2/4/8
- Built-in and Custom Programmable 24-Tap Low/High/
Band Pass Filters
- Supports Sine, LVPECL, LVDS & LVCMOS Clocks & Amplitude
Down to 400 mVPP - Clock Duty Cycle Stabilizer
- Internal Reference; Supports External Reference also
- 64-QFN Package (9mm × 9mm)
- Pin Compatible 14-bit and 12-bit Family (ADS62P4X/ADS62P2X)
ADS62P15 is a dual channel 11-bit A/D converter with maximum sample rates up to 125 MSPS. It combines high performance and low power consumption in a compact 64 QFN package. Using an internal sample and hold and low jitter clock buffer, the ADC supports high SNR and high SFDR at high input frequencies. It has coarse and fine gain options that can be used to improve SFDR performance at lower full-scale input ranges.
ADS62P15 includes a digital processing block that consists of several useful and commonly used digital functions such as ADC offset correction, fine gain correction (in steps of 0.05 dB), decimation by 2,4,8 and in-built and custom programmable filters. By default, the digital processing block is bypassed, and its functions are disabled.
Two output interface options exist – parallel CMOS and DDR LVDS (Double Data Rate). ADS62P15 includes internal references while traditional reference pins and associated decoupling capacitors have been eliminated. Nevertheless, the device can also be driven with an external reference. The device is specified over the industrial temperature range (–40°C to 85°C).
技術文件
| 重要文件 | 類型 | 標題 | 格式選項 | 下載最新的英文版本 | 日期 | |
|---|---|---|---|---|---|---|
| * | 資料表 | Dual Channel 11-Bits 125-MSPS ADC w/parallel CMOS / DDR LVDS Outputs datasheet (Rev. C) | 2012/2/9 | |||
| 應用說明 | Design Considerations for Avoiding Timing Errors during High-Speed ADC, LVDS Dat (Rev. A) | 2015/5/22 | ||||
| 應用說明 | Why Use Oversampling when Undersampling Can Do the Job? (Rev. A) | 2013/7/19 | ||||
| 應用說明 | Band-Pass Filter Design Techniques for High-Speed ADCs | 2012/2/27 | ||||
| 應用說明 | Driving High-Speed ADCs: Circuit Topologies and System-Level Parameters (Rev. A) | 2010/9/10 | ||||
| 應用說明 | Smart Selection of ADC/DAC Enables Better Design of Software-Defined Radio | 2009/4/28 | ||||
| 使用指南 | ADS62PxxEVM Quick Start Guide (Rev C Board) (Rev. A) | 2009/4/2 | ||||
| 應用說明 | CDCE62005 as Clock Solution for High-Speed ADCs | 2008/9/4 | ||||
| 應用說明 | CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital Converters | 2008/6/8 | ||||
| 應用說明 | Phase Noise Performance and Jitter Cleaning Ability of CDCE72010 | 2008/6/2 | ||||
| 應用說明 | QFN Layout Guidelines | 2006/7/28 |
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|---|---|---|
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