ADS5481
- 80/105/135-MSPS Sample Rates
- 16-Bit Resolution
- SFDR: 95 dBc at 70 MHz and 135 MSPS
- SNR: 78.6 dBFS at 70 MHz and 135 MSPS
- Efficient DDR LVDS-Compatible Outputs
- Internal Dither Available
- Total Power Dissipation: 2.2 W
- Power-Down Mode: 70 mW
- On-Chip High Impedance Analog Buffer
- QFN-64 PowerPAD Package (9 mm × 9 mm Footprint)
- Industrial Temperature Range: –40°C to +85°C
- APPLICATIONS
- Wireless Infrastructure (Multi-Carrier GSM, WCDMA, LTE)
- Test and Measurement Instrumentation
- Software-Defined Radio
- Data Acquisition
- Power Amplifier Linearization
- Communication Instrumentation
- Radar
- Medical Imaging
All trademarks are the property of their respective owners.
The ADS5481/ADS5482/ADS5483 (ADS548x) is a 16-bit family of analog-to-digital converters (ADCs) that operate from both a 5-V supply and 3.3-V supply while providing LVDS-compatible digital outputs. The ADS548x integrated analog input buffer isolates the internal switching of the onboard track and hold (T&H) from disturbing the signal source while providing a high-impedance input. An internal reference generator is also provided to simplify the system design.
Designed for highest total ENOB, the ADS548x family has outstanding low noise performance and spurious-free dynamic range.
The ADS548x is available in an QFN-64 PowerPAD package. The device is built on Texas Instruments complementary bipolar process (BiCom3) and is specified over the full industrial temperature range (–40°C to +85°C).
技術文件
| 重要文件 | 類型 | 標題 | 格式選項 | 下載最新的英文版本 | 日期 | |
|---|---|---|---|---|---|---|
| * | 資料表 | 16-Bit, 80/105/135 MSPS High-Speed ADCs datasheet (Rev. C) | 2009/10/6 | |||
| 應用說明 | Design Considerations for Avoiding Timing Errors during High-Speed ADC, LVDS Dat (Rev. A) | 2015/5/22 | ||||
| 應用說明 | Why Use Oversampling when Undersampling Can Do the Job? (Rev. A) | 2013/7/19 | ||||
| 應用說明 | High-Speed, Analog-to-Digital Converter Basics | 2012/1/11 | ||||
| 應用說明 | Input Impedance Measurement Using ADC FFT Data | 2011/1/11 | ||||
| 應用說明 | Driving High-Speed ADCs: Circuit Topologies and System-Level Parameters (Rev. A) | 2010/9/10 | ||||
| 應用說明 | Smart Selection of ADC/DAC Enables Better Design of Software-Defined Radio | 2009/4/28 | ||||
| 應用說明 | CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital Converters | 2008/6/8 | ||||
| 應用說明 | Phase Noise Performance and Jitter Cleaning Ability of CDCE72010 | 2008/6/2 | ||||
| 應用說明 | QFN Layout Guidelines | 2006/7/28 |
設計與開發
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| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| VQFN (RGC) | 64 | Ultra Librarian |