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數據轉換器
類比轉數位轉換器 (ADC)
高速 ADC (≥10 MSPS)

ADC14X250

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14 位元 250-MSPS 類比轉數位轉換器 (ADC)

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產品規格表

ADC14X250

現行
產品規格表 立即訂購

產品詳細資料

Sample rate (max) (Msps) 250 Resolution (Bits) 14 Number of input channels 1 Interface type JESD204B Analog input BW (MHz) 800 Features High Performance Rating Catalog Peak-to-peak input voltage range (V) 1.7 Power consumption (typ) (mW) 584 Architecture Pipeline SNR (dB) 71.1 ENOB (Bits) 11.5 SFDR (dB) 93 Operating temperature range (°C) -40 to 85 Input buffer Yes
Sample rate (max) (Msps) 250 Resolution (Bits) 14 Number of input channels 1 Interface type JESD204B Analog input BW (MHz) 800 Features High Performance Rating Catalog Peak-to-peak input voltage range (V) 1.7 Power consumption (typ) (mW) 584 Architecture Pipeline SNR (dB) 71.1 ENOB (Bits) 11.5 SFDR (dB) 93 Operating temperature range (°C) -40 to 85 Input buffer Yes
VQFN (RHB) 32 25 mm² 5 x 5
  • Resolution: 14-Bit
  • Conversion Rate: 250 MSPS
  • Performance:
    • Input: 240 MHz, –3 dBFS
      • SNR: 70.1 dBFS
      • Noise Spectral Density: –151.1 dBFS/Hz
      • SFDR: 87 dBFS
      • Non-HD2 and Non-HD3 SPUR: –92 dBFS
    • No Input SNR: 71.1 dBFS
  • Power Dissipation: 584 mW
  • Performance Rated up to 105°C (at thermal pad)
  • JESD204B Subclass 1 Single Lane Serial Data Interface With Lane Rate Up To 5 Gb/s
  • Buffered Analog Inputs
  • Differential Input Phase and Amplitude Correction
  • Input Sampling Clock Divider (Divide-by-1,2,4,8)
  • 4-Wire Serial Peripheral Interface (SPI)
  • 32-Pin WQFN Package (5×5 mm, 0.5-mm Pitch)
  • Resolution: 14-Bit
  • Conversion Rate: 250 MSPS
  • Performance:
    • Input: 240 MHz, –3 dBFS
      • SNR: 70.1 dBFS
      • Noise Spectral Density: –151.1 dBFS/Hz
      • SFDR: 87 dBFS
      • Non-HD2 and Non-HD3 SPUR: –92 dBFS
    • No Input SNR: 71.1 dBFS
  • Power Dissipation: 584 mW
  • Performance Rated up to 105°C (at thermal pad)
  • JESD204B Subclass 1 Single Lane Serial Data Interface With Lane Rate Up To 5 Gb/s
  • Buffered Analog Inputs
  • Differential Input Phase and Amplitude Correction
  • Input Sampling Clock Divider (Divide-by-1,2,4,8)
  • 4-Wire Serial Peripheral Interface (SPI)
  • 32-Pin WQFN Package (5×5 mm, 0.5-mm Pitch)

The ADC14X250 device is a monolithic single-channel high performance analog-to-digital converter capable of converting analog input signals into 14-bit digital words with a sampling rate of 250 MSPS. This converter uses a differential pipelined architecture with integrated input buffer to provide excellent dynamic performance and low power consumption across an extended temperature range from –40°C to 105°C as measured at the device’s PCB footprint thermal pad.

The integrated input buffer eliminates charge kickback noise coming from the internal switched capacitor sampling circuits and eases the system-level design of the driving amplifier, anti-aliasing filter, and impedance matching. The buffer can be also be adjusted to correct for phase and amplitude imbalance of the differential input signal path to improve even order harmonic distortion. An input sampling clock divider provides integer divide ratios to simplify system clocking. An integrated low-noise voltage reference eases board level design without requiring external decoupling capacitors. The output digital data is provided through a JESD204B subclass 1 single lane interface from a 32-pin, 5-mm × 5-mm WQFN package. The ADC14X250 operates on 1.2 V, 1.8 V and 3.0 V power supplies. A SPI is available to configure the device that is compatible with 1.2-V to 3-V logic.

The ADC14X250 device is a monolithic single-channel high performance analog-to-digital converter capable of converting analog input signals into 14-bit digital words with a sampling rate of 250 MSPS. This converter uses a differential pipelined architecture with integrated input buffer to provide excellent dynamic performance and low power consumption across an extended temperature range from –40°C to 105°C as measured at the device’s PCB footprint thermal pad.

The integrated input buffer eliminates charge kickback noise coming from the internal switched capacitor sampling circuits and eases the system-level design of the driving amplifier, anti-aliasing filter, and impedance matching. The buffer can be also be adjusted to correct for phase and amplitude imbalance of the differential input signal path to improve even order harmonic distortion. An input sampling clock divider provides integer divide ratios to simplify system clocking. An integrated low-noise voltage reference eases board level design without requiring external decoupling capacitors. The output digital data is provided through a JESD204B subclass 1 single lane interface from a 32-pin, 5-mm × 5-mm WQFN package. The ADC14X250 operates on 1.2 V, 1.8 V and 3.0 V power supplies. A SPI is available to configure the device that is compatible with 1.2-V to 3-V logic.
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* Data sheet ADC14X250 14-Bit 250 MSPS Single Channel ADC With 5 Gb/s JESD204B Output datasheet (Rev. B) PDF | HTML 2017年 4月 19日

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ADC14X250EVM — ADC14X250 評估模組

The ADC14X250EVM is an evaluation board used to evaluate the ADC14X250 analog-to-digital converter (ADC) from Texas Instruments. The ADC14X250 is a single channel 14-bit ADC capable of operating at sampling rates up to 250 Mega Samples Per Second (MSPS) with outputs featuring a standard JESD204B (...)

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TI204C-IP — Request for JESD204 rapid design IP

The JESD204 rapid design IP has been designed to enable FPGA engineers to achieve an accelerated path to a working JESD204 system. The IP has been architected in a way that downstream digital processing and other application logic are isolated from most of the performance- and timing-critical (...)

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DATACONVERTERPRO-SW — High Speed Data Converter Pro GUI Installer, v5.31

This high-speed data converter pro GUI is a PC (Windows® XP/7/10 compatible) program designed to aid in evaluation of most TI high-speed data converter [analog-to-digital converter (ADC) and digital-to-analog converter (DAC)] and analog front-end (AFE) platforms. Designed to support the entire (...)

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ADC14X250 IBIS Model

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PSpice® for TI 是有助於評估類比電路功能的設計和模擬環境。這款全功能設計和模擬套件使用 Cadence® 的類比分析引擎。PSpice for TI 包括業界最大的模型庫之一，涵蓋我們的類比和電源產品組合，以及特定類比行為模型，且使用無需支付費用。

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TIDEP0060 — 使用 DSP+ARM SoC 的最佳化雷達系統參考設計

對於目前使用 FPGA 或 ASIC 連接高速資料轉換器的現代雷達系統開發人員，因其需要透過提升性能並大幅降低成本、功耗和尺寸來加快上市速度，此參考設計十分適合，因為其中包括首款整合了 JESD204B 介面和數位前端 (DFE) 處理功能的廣泛可用型處理器。連接至 ADC14X250 和 DAC38J84 可為雷達、電子作戰、運算平台和轉發器等航空電子與國防應用提供高效率的解決方案。
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VQFN (RHB) 32 Ultra Librarian
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