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數據轉換器
類比轉數位轉換器 (ADC)
高速 ADC (≥10 MSPS)

ADC3660

現行

雙通道、16 位元、0.5-MSPS 至 65-MSPS、低雜訊、超低功耗類比轉數位轉換器 (ADC)

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產品規格表

ADC3660

現行
產品規格表 立即訂購

產品詳細資料

Sample rate (max) (Msps) 65 Resolution (Bits) 16 Number of input channels 2 Interface type CMOS Analog input BW (MHz) 900 Features High Performance, Low Power Rating Catalog Peak-to-peak input voltage range (V) 3.2 Power consumption (typ) (mW) 142 Architecture SAR SNR (dB) 82 ENOB (Bits) 13.3 SFDR (dB) 90 Operating temperature range (°C) -40 to 105 Input buffer No
Sample rate (max) (Msps) 65 Resolution (Bits) 16 Number of input channels 2 Interface type CMOS Analog input BW (MHz) 900 Features High Performance, Low Power Rating Catalog Peak-to-peak input voltage range (V) 3.2 Power consumption (typ) (mW) 142 Architecture SAR SNR (dB) 82 ENOB (Bits) 13.3 SFDR (dB) 90 Operating temperature range (°C) -40 to 105 Input buffer No
WQFN (RSB) 40 25 mm² 5 x 5
  • Dual channel
  • 16-bit 65 MSPS ADC (max output rate = 31 Msps)
  • Noise floor: –159 dBFS/Hz
  • Ultra-low power: 71 mW/ch at 65 MSPS
  • 16-Bit, no missing codes
  • INL: ±2 LSB; DNL: ±0.2 LSB
  • Reference: external or internal
  • Input bandwidth: 900 MHz (3 dB)
  • Industrial temperature range: –40°C to +105°C
  • On-chip digital down converter
    • Decimation by 2, 4, 8, 16, 32
    • 32-bit NCO
  • Serial CMOS interface
  • Single 1.8-V supply
  • Small footprint: 40-WQFN (5 mm × 5 mm) package
  • Spectral performance (fIN = 5 MHz):
    • SNR: 81.9 dBFS
    • SFDR: 88 dBc HD2, HD3
    • SFDR: 102 dBFS worst spur
  • Dual channel
  • 16-bit 65 MSPS ADC (max output rate = 31 Msps)
  • Noise floor: –159 dBFS/Hz
  • Ultra-low power: 71 mW/ch at 65 MSPS
  • 16-Bit, no missing codes
  • INL: ±2 LSB; DNL: ±0.2 LSB
  • Reference: external or internal
  • Input bandwidth: 900 MHz (3 dB)
  • Industrial temperature range: –40°C to +105°C
  • On-chip digital down converter
    • Decimation by 2, 4, 8, 16, 32
    • 32-bit NCO
  • Serial CMOS interface
  • Single 1.8-V supply
  • Small footprint: 40-WQFN (5 mm × 5 mm) package
  • Spectral performance (fIN = 5 MHz):
    • SNR: 81.9 dBFS
    • SFDR: 88 dBc HD2, HD3
    • SFDR: 102 dBFS worst spur

The ADC3660 device is a low-noise, ultra-low power, 16-bit, 65-MSPS dual-channel, high-speed analog-to-digital converter (ADCs). Designed for low power consumption, the device delivers a noise spectral density of –159 dBFS/Hz, combined with excellent linearity and dynamic range. The ADC3660 offers excellent dc precision, together with IF sampling support, which make the device an excellent choice for a wide range of applications. The ADC consumes only 71 mW/ch at 65 MSPS, and power consumption scales very well with lower sampling rates. In bypass mode (up to 31 MSPS) the output data is available after 1 or 2 clock cycles.

The ADC3660 uses a serial CMOS (SCMOS) interface to output the data which minimizes the number of digital interconnects. The device supports a two-lane, a one-lane and a half lane option. The serialized CMOS interface supports output rates to 250 Mbps which translates to ~ 15 MSPS (2-wire) to ~ 3.75 MSPS (0.5-wire) output rates after complex decimation. Hence the ADC3660 can be operated in ’oversampling + decimating’ mode using the internal decimation filter in order to improve the dynamic range and relax external anti-aliasing filter.

The device comes in a 40-pin WQFN package (5 mm × 5 mm) and supports the extended industrial temperature range of –40 to +105⁰C.

The ADC3660 device is a low-noise, ultra-low power, 16-bit, 65-MSPS dual-channel, high-speed analog-to-digital converter (ADCs). Designed for low power consumption, the device delivers a noise spectral density of –159 dBFS/Hz, combined with excellent linearity and dynamic range. The ADC3660 offers excellent dc precision, together with IF sampling support, which make the device an excellent choice for a wide range of applications. The ADC consumes only 71 mW/ch at 65 MSPS, and power consumption scales very well with lower sampling rates. In bypass mode (up to 31 MSPS) the output data is available after 1 or 2 clock cycles.

The ADC3660 uses a serial CMOS (SCMOS) interface to output the data which minimizes the number of digital interconnects. The device supports a two-lane, a one-lane and a half lane option. The serialized CMOS interface supports output rates to 250 Mbps which translates to ~ 15 MSPS (2-wire) to ~ 3.75 MSPS (0.5-wire) output rates after complex decimation. Hence the ADC3660 can be operated in ’oversampling + decimating’ mode using the internal decimation filter in order to improve the dynamic range and relax external anti-aliasing filter.

The device comes in a 40-pin WQFN package (5 mm × 5 mm) and supports the extended industrial temperature range of –40 to +105⁰C.
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我們的 ADC3660 系列贏得 2021 年世界電子產品成就獎 (WEAA) 放大器/資料轉換類別的年度最佳產品。

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重要文件 類型 標題 格式選項 日期
* Data sheet ADC3660 16-Bit, 0.5 to 65-MSPS, Low-Noise, Low Power Dual Channel ADC datasheet (Rev. B) PDF | HTML 2022年 3月 22日
Application note Evaluating High-Speed, RF ADC Converter Front-end Architectures PDF | HTML 2025年 3月 26日
Application note High-Speed ADC: How to Properly Terminate Single-ended CMOS Digital Outputs 2020年 12月 9日
Application note High Speed SAR ADC: Data Rate, Performance, and Pin Count Optimization PDF | HTML 2020年 12月 8日
Analog Design Journal How to simplify AFE filtering via high‐speed ADCs with internal digital filters 2020年 1月 10日

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ADC3660EVM — ADC3660 雙路、16 位元、0.5MSPS 至 65MSPS、低雜訊、超低功耗 ADC 評估模組

ADC3660 評估模組 (EVM) 專為評估 ADC3660 高速類比轉數位轉換器 (ADC) 所設計。本 EVM 搭載 ADC3660 晶片，該晶片為具備 CMOS 介面的 16 位元雙通道 ADC，最高可支援 65MSPS 運作速率。
使用指南: PDF | HTML
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DATACONVERTERPRO-SW — High Speed Data Converter Pro GUI Installer, v5.31

This high-speed data converter pro GUI is a PC (Windows® XP/7/10 compatible) program designed to aid in evaluation of most TI high-speed data converter [analog-to-digital converter (ADC) and digital-to-analog converter (DAC)] and analog front-end (AFE) platforms. Designed to support the entire (...)

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