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數據轉換器
數位轉類比轉換器 (DAC)
高速 DAC (>10 MSPS)

DAC3482

現行

雙通道、16 位元、1.25-GSPS、1x-16x 內插數位轉類比轉換器 (DAC)

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產品規格表

DAC3482

現行
產品規格表 立即訂購

產品詳細資料

Resolution (Bits) 16 Number of DAC channels 2 Interface type Parallel LVDS Sample/update rate (Msps) 1250 Features Ultra High Speed Rating Catalog Interpolation 16x, 1x, 2x, 4x, 8x Power consumption (typ) (mW) 800 SFDR (dB) 82 Architecture Current Source Operating temperature range (°C) -40 to 85 Reference type Int
Resolution (Bits) 16 Number of DAC channels 2 Interface type Parallel LVDS Sample/update rate (Msps) 1250 Features Ultra High Speed Rating Catalog Interpolation 16x, 1x, 2x, 4x, 8x Power consumption (typ) (mW) 800 SFDR (dB) 82 Architecture Current Source Operating temperature range (°C) -40 to 85 Reference type Int
NFBGA (ZAY) 196 144 mm² 12 x 12 WQFN-MR (RKD) 88 81 mm² 9 x 9
  • Very low power: 900mW at 1.25GSPS, full operating conditions
  • Multi-DAC synchronization
  • Selectable 2x, 4x, 8x, 16x interpolation filter
    • Stop-band attenuation > 90dBc
  • Flexible on-chip complex mixing
    • Fine mixer with 32-bit NCO
    • Power saving coarse mixer: ± n×Fs/8
  • High performance, low jitter clock multiplying PLL
  • Digital I and Q correction
    • Gain, phase, offset, and group delay correction
  • Digital inverse sinc filter
  • Flexible LVDS input data bus
    • Word- or byte-wide interface
    • 8 Sample input FIFO
    • Data pattern checker
    • Parity check
  • Temperature sensor
  • Differential scalable output: 10mA to 30mA
  • Multiple package options: 88 Pin 9 x 9mm WQFN-MR and 196-ball 12mm x12mm
  • Very low power: 900mW at 1.25GSPS, full operating conditions
  • Multi-DAC synchronization
  • Selectable 2x, 4x, 8x, 16x interpolation filter
    • Stop-band attenuation > 90dBc
  • Flexible on-chip complex mixing
    • Fine mixer with 32-bit NCO
    • Power saving coarse mixer: ± n×Fs/8
  • High performance, low jitter clock multiplying PLL
  • Digital I and Q correction
    • Gain, phase, offset, and group delay correction
  • Digital inverse sinc filter
  • Flexible LVDS input data bus
    • Word- or byte-wide interface
    • 8 Sample input FIFO
    • Data pattern checker
    • Parity check
  • Temperature sensor
  • Differential scalable output: 10mA to 30mA
  • Multiple package options: 88 Pin 9 x 9mm WQFN-MR and 196-ball 12mm x12mm

The DAC3482 is a very low power, high dynamic range, dual-channel, 16-bit digital-to-analog converter (DAC) with a sample rate as high as 1.25GSPS.

The device includes features that simplify the design of complex transmit architectures: 2x to 16x digital interpolation filters with over 90dB of stop-band attenuation simplify the data interface and reconstruction filters. A complex mixer allows flexible carrier placement. A high-performance low jitter clock multiplier simplifies clocking of the device without significant impact on the dynamic range. The digital Quadrature Modulator Correction (QMC) enables complete IQ compensation for gain, offset, phase, and group delay between channels in direct up-conversion applications.

Digital data is input to the device through a flexible LVDS data bus with on-chip termination. Data can be input either word-wide or byte-wide. The device includes a FIFO, data pattern checker and parity test to ease the input interface. The interface also allows full synchronization of multiple devices.

The device is characterized for operation over the entire industrial temperature range of –40°C to 85°C and is available in a small 88 pin 9 x 9mm WQFN-MR package or 196-ball 12 x12mm NFBGA package.

Low power, small size, superior crosstalk, high dynamic range, and features of the DAC3482 make it an ideal fit for today’s communication systems.

The DAC3482 is a very low power, high dynamic range, dual-channel, 16-bit digital-to-analog converter (DAC) with a sample rate as high as 1.25GSPS.

The device includes features that simplify the design of complex transmit architectures: 2x to 16x digital interpolation filters with over 90dB of stop-band attenuation simplify the data interface and reconstruction filters. A complex mixer allows flexible carrier placement. A high-performance low jitter clock multiplier simplifies clocking of the device without significant impact on the dynamic range. The digital Quadrature Modulator Correction (QMC) enables complete IQ compensation for gain, offset, phase, and group delay between channels in direct up-conversion applications.

Digital data is input to the device through a flexible LVDS data bus with on-chip termination. Data can be input either word-wide or byte-wide. The device includes a FIFO, data pattern checker and parity test to ease the input interface. The interface also allows full synchronization of multiple devices.

The device is characterized for operation over the entire industrial temperature range of –40°C to 85°C and is available in a small 88 pin 9 x 9mm WQFN-MR package or 196-ball 12 x12mm NFBGA package.

Low power, small size, superior crosstalk, high dynamic range, and features of the DAC3482 make it an ideal fit for today’s communication systems.
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技術文件

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重要文件 類型 標題 格式選項 日期
* Data sheet DAC3482, Dual-Channel, 16-Bit, 1.25GSPS Digital-to-Analog Converter (DAC) datasheet (Rev. G) PDF | HTML 2024年 1月 18日
Application note QFN and SON PCB Attachment (Rev. C) PDF | HTML 2023年 12月 6日
Application note Effects of Clock Spur on High Speed DAC Performance (Rev. A) 2015年 5月 18日
Design guide TSW308x Wideband Digital to RF Transmit Solution Design Guide 2013年 9月 3日
Design guide Analog Interfacing Networks for DAC348x and Modulators (TIDA-00077) (Rev. A) 2013年 8月 14日
Application note Using DAC348x with Fault Detection and Auto Output Shut-off Feature 2013年 2月 21日
Application note DAC348x Device Configuration and Synchronization 2013年 2月 18日
Application note Effects of Clock Noise on High Speed DAC Performance 2012年 11月 8日
Application note High Speed, Digital-to-Analog Converters Basics (Rev. A) 2012年 10月 23日
Application note Design Summary Multi-row Quad Flat No-lead (MRQFN) 2012年 8月 29日
User guide Interfacing Altera FPGAs to ADS4249 and DAC3482 (TIDA-00069 Reference Guide) 2012年 7月 10日
User guide TSW1400 Pattern Generators 2012年 5月 3日
Application note Configuring and Optimizing On-Chip PLL of the DAC348x 2012年 1月 26日
User guide TSW3085EVM ACPR and EVM Measurements (TIDA-00076 Reference Guide) 2011年 12月 29日

設計與開發

如需其他條款或必要資源，請按一下下方的任何標題以檢視詳細頁面 (如有)。

開發板

TSW3085EVM — 寬頻發射訊號鏈評估板和參考設計

The TSW3085 Evalutaion Module is a circuit board that allows system designers to evaluate the combined performance of Texas Instruments' transmit signal chain with the LMK04806B (formally National Semiconductor) low noise clock generator/jitter cleaner. For ease of use as a complete RF transmit (...)

使用指南: PDF
TI.com 無法提供
開發模組 (EVM) 的 GUI

DATACONVERTERPRO-SW — High Speed Data Converter Pro GUI Installer, v5.31

This high-speed data converter pro GUI is a PC (Windows® XP/7/10 compatible) program designed to aid in evaluation of most TI high-speed data converter [analog-to-digital converter (ADC) and digital-to-analog converter (DAC)] and analog front-end (AFE) platforms. Designed to support the entire (...)

支援產品和硬體

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開發模組 (EVM) 的 GUI

SLAC483 — DAC348x EVM Software GUI

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支援產品和硬體
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開發模組 (EVM) 的 GUI

SLAC507 — TSW308x EVM Software

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支援產品和硬體
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開發模組 (EVM) 的 GUI

SLLC420 — TSW3100EVM GUI v2.7

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支援產品和硬體
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模擬型號

DAC3482 IBIS Model (Rev. A)

SLAM073A.ZIP (33 KB) - IBIS Model
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模擬型號

TINA-TI SPICE Models: Analog Interfacing Networks for DAC348x and Modulators

SLUC481.ZIP (198 KB) - TINA-TI Spice Model
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配置圖

TSW3085EVM Design Package Board rev B

SLAR058.ZIP (4917 KB)
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配置圖

TSW3100 Design Package

SLLC424.ZIP (15830 KB)
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模擬工具

PSPICE-FOR-TI — PSpice® for TI 設計與模擬工具

PSpice® for TI 是有助於評估類比電路功能的設計和模擬環境。這款全功能設計和模擬套件使用 Cadence® 的類比分析引擎。PSpice for TI 包括業界最大的模型庫之一，涵蓋我們的類比和電源產品組合，以及特定類比行為模型，且使用無需支付費用。

PSpice for TI 設計和模擬環境可讓您使用其內建函式庫來模擬複雜的混合訊號設計。在進行佈局和製造之前，建立完整的終端設備設計和解決方案原型，進而縮短上市時間並降低開發成本。 

在 PSpice for TI 設計與模擬工具中，您可以搜尋 TI (...)
要求
參考設計

TIDA-00077 — 適用於 DAC348x 和調變器的類比介面網路

The analog interface circuits in this reference design are often used between current-source based digital-to analog converters (DAC) and quadrature modulators. While the DAC348x is used as an example of a TI high-speed DAC, the circuits can be applied to other current-source based converters with (...)
Design guide: PDF
電路圖: PDF
參考設計

TIDA-00076 — 相鄰通道功率比 (ACPR) 和誤差向量幅度 (%EVM) 量測

This reference design discusses the use of the TSW3085EVM with the TSW3100 pattern generator to test adjacent channel power ratio (ACPR) and error vector magnitude (EVM) measurements of LTE baseband signals. By using the TSW3100 LTE GUI, patterns are loaded into the TSW3085EVM which is comprised of (...)
使用指南: PDF
電路圖: PDF
參考設計

TIDA-00069 — 說明如何將 Altera FPGA 介接至高速 LVDS 介面數據轉換器的 FPGA 韌體範例

This reference design and the associated example Verilog code can be used as a starting point for interfacing Altera FPGAs to Texas Instruments' high-speed LVDS-interface analog-to-digital converters (ADC) and digital-to-analog converters (DAC). The firmware implementation is explained and the (...)
使用指南: PDF
電路圖: PDF
封裝 針腳 CAD 符號、佔位空間與 3D 模型
NFBGA (ZAY) 196 Ultra Librarian
WQFN-MR (RKD) 88 Ultra Librarian
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