ADS58B18
- ADS58B18: 11-Bit, 200MSPS
- ADS58B19: 9-Bit, 250MSPS
- Integrated High-Impedance Analog Input Buffer
- Ultralow Power:
- Analog Power: 258mW at 200MSPS
- I/O Power: 69mW (DDR LVDS, low LVDS swing)
- High Dynamic Performance:
- ADS58B18: 66dBFS SNR and 81dBc SFDR at 150MHz
- ADS58B19: 55.7dBFS SNR and 76dBc SFDR at 150MHz
- Enhanced SNR Using TI-Proprietary SNRBoost Technology (ADS58B18 Only)
- –77.7dBFS SNR in 20MHz Bandwidth
- Dynamic Power Scaling with Sample Rate
- Output Interface:
- Double Data Rate (DDR) LVDS with Programmable Swing and Strength
- Standard Swing: 350mV
- Low Swing: 200mV
- Default Strength: 100Ω Termination
- 2x Strength: 50Ω Termination
- 1.8V Parallel CMOS Interface Also Supported
- Double Data Rate (DDR) LVDS with Programmable Swing and Strength
- Programmable Gain for SNR/SFDR Trade-Off
- DC Offset Correction
- Supports Low Input Clock Amplitude
- Package: QFN-48 (7mm × 7mm)
PowerPAD is a trademark of Texas Instruments Incorporated.
All other trademarks are the property of their respective owners.
The ADS58B18/B19 are members of the ultralow power ADS4xxx analog-to-digital converter (ADC) family that features integrated analog buffers and SNRBoost technology. The ADS58B18 and ADS58B19 are 11-bit and 9-bit ADCs with sampling rates up to 200MSPS and 250MSPS, respectively. Innovative design techniques are used to achieve high dynamic performance while consuming extremely low power. The analog input pins have buffers with constant performance and input impedance across a wide frequency range. This architecture makes these parts well-suited for multi-carrier, wide bandwidth communications applications such as PA linearization.
The ADS58B18 uses TI-proprietary SNRBoost technology that can be used to overcome SNR limitation as a result of quantization noise for bandwidths less than Nyquist (fS/2).
Both devices have gain options that can be used to improve SFDR performance at lower full-scale input ranges, especially at very high input frequencies. They also include a dc offset correction loop that can be used to cancel the ADC offset. At lower sampling rates, the ADC automatically operates at scaled-down power with no loss in performance.
These devices support both double data rate (DDR) low-voltage differential signaling (LVDS) and parallel CMOS digital output interfaces. The low data rate of the DDR LVDS interface (maximum 500Mbps) makes it possible to use low-cost field-programmable gate array (FPGA)-based receivers. They have a low-swing LVDS mode that can be used to further reduce the power consumption. The strength of the LVDS output buffers can also be increased to support 50Ω differential termination.
The ADS58B18/B19 are both available in a compact QFN-48 package and specified over the industrial temperature range (–40°C to +85°C).
技術文件
| 重要文件 | 類型 | 標題 | 格式選項 | 下載最新的英文版本 | 日期 | |
|---|---|---|---|---|---|---|
| * | 資料表 | 11-Bit, 200MSPS/9-Bit, 250MSPS, Ultralow-Power ADCs with Analog Buffer datasheet (Rev. D) | 2011/1/28 | |||
| * | 使用指南 | Interfacing Altera FPGAs to ADS4249 and DAC3482 (TIDA-00069 Reference Guide) | 2012/7/10 | |||
| 應用說明 | High-Speed, Analog-to-Digital Converter Basics | 2012/1/11 | ||||
| 應用說明 | Power Supply Design for the ADS41xx (Rev. A) | 2011/12/29 | ||||
| 應用說明 | Driving High-Speed ADCs: Circuit Topologies and System-Level Parameters (Rev. A) | 2010/9/10 | ||||
| 應用說明 | Smart Selection of ADC/DAC Enables Better Design of Software-Defined Radio | 2009/4/28 | ||||
| 應用說明 | CDCE62005 as Clock Solution for High-Speed ADCs | 2008/9/4 | ||||
| 應用說明 | CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital Converters | 2008/6/8 | ||||
| 應用說明 | Phase Noise Performance and Jitter Cleaning Ability of CDCE72010 | 2008/6/2 | ||||
| 應用說明 | QFN Layout Guidelines | 2006/7/28 |
設計與開發
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ADS58B18EVM — ADS58B18 11 位元、200-MSPS 類比轉數位轉換器評估模組
ADS58B18EVM 是一款電路板，可讓設計人員評估德州儀器 ADS58B18 裝置 (一款功耗極低的 11 位元 200 MSPS 類比數位轉換器) 的效能。ADC 具有緩衝類比輸入及可配置的並行 DDR LVDS 或 CMOS 輸出。EVM 提供了可在各種時鐘、輸入和電源條件下測試 ADS58B18 的靈活環境。
ADS58B18EVM 還包括德州儀器的新款 10 輸出低抖動時鐘同步器和抖動消除器裝置 - CDCE72010，可用於驅動 ADS58B18 的時鐘輸入。我們為外部 VCXO 和晶體帶通濾波器提供了開放式插槽，允許對組合的高性能 ADC 與時鐘電路 (...)
DATACONVERTERPRO-SW — 高速資料轉換器 Pro GUI 安裝程式，v5.31
這款高速資料轉換器專業 GUI 是一款 PC（與 Windows® XP/7/10 相容）程式，旨在協助評估大多數 TI 高速資料轉換器 [類比轉數位轉換器 (ADC) 和數位轉類比轉換器 (DAC)] 和類比前端 (AFE) 平台。DATACONVERTERPRO-SW 旨在支援整個 TSW14xxx 系列資料擷取和模式產生卡，為時域和頻域中的資料轉換器分析提供強大且快速的解決方案，並支援單音、多音和調變訊號。此 GUI 也與 TI 模式產生 GUI 相容，可快速合成單音、多音和調變訊號。
使用者可以向 DATACONVERTERPRO-SW 提供自訂模式，以載入到 TI DAC。支援從 (...)
SLAC384 — ADS41xx SPI GUI rev1.6
ANALOG-ENGINEER-CALC — PC software analog engineer's calculator
類比工程師的計算機旨在加速類比電路設計工程師定期使用的許多重複計算。此基於 PC 的工具提供圖形介面，列出各種常見計算，從使用回饋電阻器設定運算放大器增益到選擇適當的電路設計元件以穩定類比數位轉換器 (ADC) 驅動緩衝電路。
除了作為獨立工具使用外，此計算機還與類比工程師口袋參考中描述的概念相得益彰。
JITTER-SNR-CALC — Jitter and SNR calculator
JITTER-SNR-CALC can be used for calculating theoretical Signal to Noise (SNR) performance of ADCs based on input frequency and clock jitter.
| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| VQFN (RGZ) | 48 | Ultra Librarian |
訂購與品質
建議產品可能具有與此 TI 產品相關的參數、評估模組或參考設計。