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RF 接收器

ADS62PF49

現行

雙通道 250MSPS 回饋接收器 IC

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ADS62PF49

現行
產品規格表 立即訂購

產品詳細資料

Number of input channels 2 Resolution (Bits) 14 Sample rate (max) (Msps) 250 Features Decimating Filter, Differential Inputs, High Dynamic Range, Nap Mode, Out of Range Indicator, Power Down Analog input BW (MHz) 800 Power consumption (typ) (mW) 1250 Operating temperature range (°C) -40 to 85 Rating Catalog
Number of input channels 2 Resolution (Bits) 14 Sample rate (max) (Msps) 250 Features Decimating Filter, Differential Inputs, High Dynamic Range, Nap Mode, Out of Range Indicator, Power Down Analog input BW (MHz) 800 Power consumption (typ) (mW) 1250 Operating temperature range (°C) -40 to 85 Rating Catalog
VQFN (RGC) 64 81 mm² 9 x 9
  • Maximum Output Sample Rate: 250 MSPS
  • Pin-Compatible with ADS62P49
  • Variable Output Resolution
    • High Resolution Burst Mode with 14-Bit Output: 73 dB SNR at Low IF,
      70.5 dB SNR at 170 MHz
    • Low Resolution with 9-Bit 250 MSPS or 11-Bit 125 MSPS
  • Double Data Rate (DDR) LVDS Output
  • Programmable Gain up to 6 dB for SNR/SFDR Trade-off
  • 90-dB Cross-Talk
  • Power Consumption of 1.25 W
  • 64-Pin QFN Package (9 mm × 9 mm)
  • APPLICATIONS
    • Feedpath Path for Multi-Carrier, Multi-Mode Cellular Infrastructure Base Stations
    • Maximum Output Sample Rate: 250 MSPS
    • Pin-Compatible with ADS62P49
    • Variable Output Resolution
      • High Resolution Burst Mode with 14-Bit Output: 73 dB SNR at Low IF,
        70.5 dB SNR at 170 MHz
      • Low Resolution with 9-Bit 250 MSPS or 11-Bit 125 MSPS
    • Double Data Rate (DDR) LVDS Output
    • Programmable Gain up to 6 dB for SNR/SFDR Trade-off
    • 90-dB Cross-Talk
    • Power Consumption of 1.25 W
    • 64-Pin QFN Package (9 mm × 9 mm)
  • APPLICATIONS
    • Feedpath Path for Multi-Carrier, Multi-Mode Cellular Infrastructure Base Stations

    The ADS62PF49 is a dual-channel feedback reciever IC with sampling rates up to 250 MSPS. It allows a high-resolution, 14-bit output for a limited time followed by a low-resolution mode with a minimum of 8x longer time. It is pin-compatible to the ADS62P49 and ADS62C17 dual ADCs.

    The ADS62PF49 has gain options that can be used to improve SFDR performance at lower full-scale input ranges. It includes a dc offset correction loop that can be used to cancel the analog-to-digital conversion (ADC) offset.

    It includes internal references while the traditional reference pins and associated decoupling capacitors have been eliminated. The device is specified over the industrial temperature range (–40°C to 85°C).

    The ADS62PF49 is a dual-channel feedback reciever IC with sampling rates up to 250 MSPS. It allows a high-resolution, 14-bit output for a limited time followed by a low-resolution mode with a minimum of 8x longer time. It is pin-compatible to the ADS62P49 and ADS62C17 dual ADCs.

    The ADS62PF49 has gain options that can be used to improve SFDR performance at lower full-scale input ranges. It includes a dc offset correction loop that can be used to cancel the analog-to-digital conversion (ADC) offset.

    It includes internal references while the traditional reference pins and associated decoupling capacitors have been eliminated. The device is specified over the industrial temperature range (–40°C to 85°C).
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    重要文件 類型 標題 格式選項 日期
    * Data sheet Dual-Channel, 250-MSPS Feedback Receiver IC datasheet 2011年 6月 24日
    Application note Design Considerations for Avoiding Timing Errors during High-Speed ADC, LVDS Dat (Rev. A) 2015年 5月 22日
    Application note Why Use Oversampling when Undersampling Can Do the Job? (Rev. A) 2013年 7月 19日

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