開發模組 (EVM) 的 GUI
ADS58C48SPI-SW — ADS58C48 SPI Software
The ADS58C28 EVM software GUI allows for programming control of the ADS58C48.
ADS58C48
- Maximum Sample Rate: 200 MSPS
- High Dynamic Performance
- SFDR 82 dBc at 140 MHz
- 72.3 dBFS SNR in 60 MHz BW Using SNRBoost3G technology
- SNRBoost3G Highlights
- Supports Wide Bandwidth up to 60 MHz
- Programmable Bandwidths – 60 MHz, 40 MHz, 30 MHz, 20 MHz
- Flat Noise Floor within the Band
- Independent SNRBoost3G Coefficients for Every Channel
- Output Interface
- Double Data Rate (DDR) LVDS with Programmable Swing and Strength
- Standard Swing: 350mV
- Low Swing: 200mV
- Default Strength: 100
Termination - 2x Strength: 50 Termination
- 1.8V Parallel CMOS Interface Also Supported
- Double Data Rate (DDR) LVDS with Programmable Swing and Strength
- Ultra-Low Power with Single 1.8V Supply
- 0.9W Total Power
- 1.32 W Total Power (200 MSPS) with SNRBoost3G on all 4 Channels
- 1.12 W Total Power (200 MSPS) with SNRBoost3G on 2 Channels
- Programmable Gain up to 6dB for SNR/SFDR Trade-Off
- DC Offset Correction
- Supports Low Input Clock Amplitude
- 80-TQFP Package
The ADS58C48 is a quad channel 11-bit A/D converter with sampling rate up to 200 MSPS. It uses innovative design techniques to achieve high dynamic performance, while consuming extremely low power at 1.8V supply. This makes it well-suited for multi-carrier, wide band-width communications applications.
The ADS58C48 uses third-generation SNRBoost3G technology to overcome SNR limitation due to quantization noise (for bandwidths < Nyquist, Fs/2). Enhancements in the SNRBoost3G technology allow support for SNR improvements over wide bandwidths (up to 60 MHz). In addition, separate SNRBoost3G coefficients can be programmed for each channel.
The device has digital gain function that can be used to improve SFDR performance at lower full-scale input ranges. It includes a dc offset correction loop that can be used to cancel the ADC offset.
The digital outputs of all channels are output as DDR LVDS (Double Data Rate) together with an LVDS clock output. The low data rate of this interface (400Mbps at 200 MSPS sample rate) makes it possible to use low-cost FPGA-based receivers. The strength of the LVDS output buffers can be increased to support 50 ohms differential termination. This allows the output clock signal to be connected to two separate receiver chips with an effective 50 termination (such as the two clock ports of the GC5330).
The same digital output pins can also be configured as a parallel 1.8V CMOS interface.
It includes internal references while the traditional reference pins and associated decoupling capacitors have been eliminated. The device is specified over the industrial temperature range (–40°C to 85°C).
技術文件
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檢視所有 11 | 重要文件 | 類型 | 標題 | 格式選項 | 日期 |
|---|---|---|---|---|
| * | Data sheet | Quad Channel IF Receiver with SNRBoost 3G datasheet | 2010年 5月 27日 | |
| Application note | Band-Pass Filter Design Techniques for High-Speed ADCs | 2012年 2月 27日 | ||
| Application note | High-Speed, Analog-to-Digital Converter Basics | 2012年 1月 11日 | ||
| Application note | Power Supply Design for the ADS41xx (Rev. A) | 2011年 12月 29日 | ||
| Application note | Understanding Low-Amplitude Behavior of 11-bit ADCs | 2011年 10月 22日 | ||
| Application note | Driving High-Speed ADCs: Circuit Topologies and System-Level Parameters (Rev. A) | 2010年 9月 10日 | ||
| Application note | Using Windowing With SNRBoost 3G Technology | 2010年 8月 30日 | ||
| Application note | Smart Selection of ADC/DAC Enables Better Design of Software-Defined Radio | 2009年 4月 28日 | ||
| Application note | CDCE62005 as Clock Solution for High-Speed ADCs | 2008年 9月 4日 | ||
| Application note | CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital Converters | 2008年 6月 8日 | ||
| Application note | Phase Noise Performance and Jitter Cleaning Ability of CDCE72010 | 2008年 6月 2日 |
設計與開發
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開發板
ADS58C28EVM — ADS58C28 雙通道、11 位元、200-MSPS 類比轉數位轉換器評估模組
ADS58C28EVM 是能讓設計人員評估德州儀器 (TI) ADS58C28 裝置 (具有 SNRBoost 技術的雙通道 11 位元 200 MSPS 類比轉換器) 性能的電路板。ADC EVM 具有 DDR LVDS 資料輸出，與 TI 的 TSW1200 資料擷取卡相容，可進行快速評估。EVM 提供了可在各種時鐘、輸入和電源條件下測試 ADS58C28 的靈活環境。
評估模組的設計是在轉換器的四個輸入，每個輸入都有背對背高頻寬平衡不平衡轉換器。如此即可將廣泛的單端輸入訊號掃頻輸入至 ADC 的任何通道。 ADS58C28EVM 也與 FMC-ADC- 轉接器和 (...)
使用指南: PDF
開發模組 (EVM) 的 GUI
DATACONVERTERPRO-SW — High Speed Data Converter Pro GUI Installer, v5.31
This high-speed data converter pro GUI is a PC (Windows® XP/7/10 compatible) program designed to aid in evaluation of most TI high-speed data converter [analog-to-digital converter (ADC) and digital-to-analog converter (DAC)] and analog front-end (AFE) platforms. Designed to support the entire (...)
支援產品和硬體
支援軟體
SBAC120 — TIGAR Support Files
支援產品和硬體
計算工具
ANALOG-ENGINEER-CALC — PC software analog engineer's calculator
The analog engineer’s calculator is designed to speed up many of the repetitive calculations that analog circuit design engineers use on a regular basis. This PC-based tool provides a graphical interface with a list of various common calculations ranging from setting operational-amplifier (...)
支援產品和硬體
計算工具
JITTER-SNR-CALC — Jitter and SNR calculator
JITTER-SNR-CALC can be used for calculating theoretical Signal to Noise (SNR) performance of ADCs based on input frequency and clock jitter.
支援產品和硬體
設計工具
SBAC119 — TIGAR (Texas Instruments Graphical Evaluation of ADC Response Tool)
支援產品和硬體
模擬工具
PSPICE-FOR-TI — PSpice® for TI 設計與模擬工具
PSpice® for TI 是有助於評估類比電路功能的設計和模擬環境。這款全功能設計和模擬套件使用 Cadence® 的類比分析引擎。PSpice for TI 包括業界最大的模型庫之一，涵蓋我們的類比和電源產品組合，以及特定類比行為模型，且使用無需支付費用。
PSpice for TI 設計和模擬環境可讓您使用其內建函式庫來模擬複雜的混合訊號設計。在進行佈局和製造之前，建立完整的終端設備設計和解決方案原型，進而縮短上市時間並降低開發成本。
在 PSpice for TI 設計與模擬工具中，您可以搜尋 TI (...)
PSpice for TI 設計和模擬環境可讓您使用其內建函式庫來模擬複雜的混合訊號設計。在進行佈局和製造之前，建立完整的終端設備設計和解決方案原型，進而縮短上市時間並降低開發成本。
在 PSpice for TI 設計與模擬工具中，您可以搜尋 TI (...)
| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| HTQFP (PFP) | 80 | Ultra Librarian |
訂購與品質
內含資訊：
- RoHS
- REACH
- 產品標記
- 鉛塗層/球物料
- MSL 等級/回焊峰值
- MTBF/FIT 估算值
- 材料內容
- 認證摘要
- 進行中的可靠性監測
內含資訊：
- 晶圓廠位置
- 組裝地點
建議產品可能具有與此 TI 產品相關的參數、評估模組或參考設計。