ADS8910B
- Resolution: 18-Bits
- High Sample Rate With No Latency Output:
- ADS8910B: 1-MSPS
- ADS8912B: 500-kSPS
- ADS8914B: 250-kSPS
- Integrated LDO Enables Single-Supply Operation
- Low-Power Reference Buffer With No Droop
- Excellent AC and DC
Performance:
- SNR: 102.5-dB, THD: –125-dB
- INL: ±0.5-LSB
- DNL: ±0.2-LSB, 18-Bit No-Missing-Codes
- Wide Input
Range:
- Unipolar Differential Input Range: ±VREF
- VREF Input Range: 2.5-V to 5-V
- Single-Supply, Low-Power
Operation
(Includes Internal Reference Buffer and LDO)- ADS8910B : 21-mW at 1-MSPS
- ADS8912B : 16-mW at 500-kSPS
- ADS8914B : 14-mW at 250-kSPS
- Enhanced-SPI Digital Interface
- Interface SCLK: 20-MHz at 1-MSPS
- Configurable Data Parity Output
- Extended Temperature Range: –40°C to +125°C
- Small Footprint: 4-mm × 4-mm VQFN
The ADS8910B, ADS8912B, and ADS8914B (ADS891xB) belong to a family of pin-to-pin compatible, high-speed, single-channel, high-precision, 18-bit successive approximation register (SAR) analog-to-digital convertors (ADCs) with an integrated reference buffer and integrated low-dropout regulator (LDO). The device family includes the ADS890xB (20-bit) and ADS892xB (16-bit) resolution variants.
The ADS891xB boost analog performance while maintaining high-resolution data transfer by using TI’s enhanced-SPI feature. Enhanced-SPI enables the ADS89xxB to achieve high throughput at lower clock speeds, thereby simplifying the board layout and lowering system cost. Enhanced-SPI also simplifies clocking-in of data, thereby making this device an excellent choice for applications involving FPGAs, DSPs. The ADS89xxB is compatible with a standard SPI Interface.
The ADS891xB has an internal data parity feature that can be appended to the ADC data output. ADC data validation by the host, using parity bits, improves system reliability.
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具備升級功能，可直接投入使用替代所比較的裝置。
技術文件
| 重要文件 | 類型 | 標題 | 格式選項 | 下載最新的英文版本 | 日期 | |
|---|---|---|---|---|---|---|
| * | 資料表 | ADS891xB 18-Bit, High-Speed SAR ADCs With Integrated Reference Buffer and Enhanced Performance Features datasheet (Rev. B) | PDF | HTML | 2018/1/26 | ||
| Circuit design | High-current battery monitor circuit: 0–10A, 0-10kHz, 18 bit (Rev. A) | PDF | HTML | 2024/9/12 | |||
| Circuit design | High-voltage battery monitor circuit: ±20V, 0–10kHz, 18-bit fully differential (Rev. B) | PDF | HTML | 2024/9/11 | |||
| 應用說明 | Attenuator Amplifier Design to Maximize the Input Voltage of Differential ADCs | 2018/6/14 | ||||
| Application brief | Improving Input Settling for Precision Data Converters | 2017/12/12 | ||||
| Application brief | Optimizing Data Transfer on High-Resolution, High-Throughput Data Converters | 2017/12/12 | ||||
| Application brief | Simplify Isolation Designs Using an Enhanced-SPI ADC Interface | 2017/12/11 | ||||
| 白皮書 | Enabling Faster, Smarter, and More Robust Solutions for SAR ADSx With multiSPI | 2016/11/8 | ||||
| 更多文件說明 | ADS8910EVM-PDK Quick Start Guide | 2016/3/16 |
設計與開發
如需其他條款或必要資源，請按一下下方的任何標題以檢視詳細頁面 (如有)。
ADS8900BEVM-PDK — ADS8900B 全差動輸入、20 位元 SAR ADC EVM 性能展示套件 (PDK)
ADS8900B 評估模組 (EVM) 和性能展示套件 (PDK) 是評估 ADS8900B 連續近似暫存器 (SAR) 類比轉數位轉換器 (ADC) 效能的平台、這是一款全差動輸入、20 位元、1MSPS 裝置。ADS8900BEVM-PDK 包括 ADS8900B EVM 板和精密主機介面 (PHI) 控制器板，可啟用隨附的電腦軟體。
SBAC183 — Source Files for SBAA267
±50mA to ±10A, 0V to 75V Common-Mode TINA-TI Spice Model
ANALOG-ENGINEER-CALC — PC software analog engineer's calculator
類比工程師的計算機旨在加速類比電路設計工程師定期使用的許多重複計算。此基於 PC 的工具提供圖形介面，列出各種常見計算，從使用回饋電阻器設定運算放大器增益到選擇適當的電路設計元件以穩定類比數位轉換器 (ADC) 驅動緩衝電路。
除了作為獨立工具使用外，此計算機還與類比工程師口袋參考中描述的概念相得益彰。
ADC-DAC-TO-VREF-SELECT-DESIGN-TOOL — The ADC-TO-VREF-SELECT tool enables the pairing of TI ADCs, DACs, and series voltage references.
TIDA-01050 — 適用於 18 位元 SAR 資料轉換器的最佳化類比前端 DAQ 系統參考設計
TIDA-01051 — 針對自動測試設備最佳化 FPGA 利用率和數據處理能力的參考設計
TIDA-01052 — 使用負電源輸入改進全幅 THD 的 ADC 驅動器參考設計
TIDA-060017 — 透過 LVDS 介面傳輸 SPI 訊號參考設計
TIPD211 — 適用於測試與量測應用的 20 位元、1 MSPS、四通道小型設計參考設計
| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| VQFN (RGE) | 24 | Ultra Librarian |
訂購與品質
建議產品可能具有與此 TI 產品相關的參數、評估模組或參考設計。