The ADC32RF45 device is a 14-bit, 3.0-GSPS, dual-channel, analog-to-digital converter (ADC) that supports RF sampling with input frequencies up to 4 GHz and beyond. Designed for high signal-to-noise ratio (SNR), the ADC32RF45 delivers a noise spectral density of –155 dBFS/Hz as well as dynamic range and channel isolation over a large input frequency range. The buffered analog input with on-chip termination provides uniform input impedance across a wide frequency range and minimizes sample-and-hold glitch energy.
Each ADC channel can be connected to a dual-band, digital down-converter (DDC) with up to three independent, 16-bit numerically-controlled oscillators (NCOs) per DDC for phase-coherent frequency hopping. Additionally, the ADC is equipped with front-end peak and RMS power detectors and alarm functions to support external automatic gain control (AGC) algorithms.
The ADC32RF45 supports the JESD204B serial interface with subclass 1-based deterministic latency using data rates up to 12.5 Gbps with up to four lanes per ADC. The device is offered in a 72-pin VQFN package (10 mm × 10 mm) and supports the industrial temperature range (–40°C to +85°C).
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TSW40RF80 評估模組 (EVM) 是二發射二接收 (2T2R) 射頻取樣收發器參考設計。本模組包含 DAC38RF80 雙通道射頻取樣數位轉類比轉換器 (DAC) 及 ADC32RF45 雙通道射頻取樣類比轉數位轉換器 (ADC)。
DAC38RF80 取樣率最高可運作 9 GSPS，包括用於產生高頻時鐘的板載 PLL/VCO。輸出為單端，可輕鬆從介面連接 50-Ω 電路。ADC32RF45 取樣率最高可運作 3 GSPS。可選擇在各通道中使用雙數位降壓轉換器，或繞過轉換器以存取完整 Nyquist 頻寬。
TSW40RF80EVM 包含 LMK04828 時脈產生器，用於為 DAC (...)
The JESD204 rapid design IP has been designed to enable FPGA engineers to achieve an accelerated path to a working JESD204 system. The IP has been architected in a way that downstream digital processing and other application logic are isolated from most of the performance- and timing-critical (...)
This high-speed data converter pro GUI is a PC (Windows® XP/7/10 compatible) program designed to aid in evaluation of most TI high-speed data converter [analog-to-digital converter (ADC) and digital-to-analog converter (DAC)] and analog front-end (AFE) platforms. Designed to support the entire (...)
This Excel calculator provides system designers a way to simplify the design and debugging of direct RF-sampling receivers. It offers three functions: frequency planning, analog filtering, and decimation filter spur location.
In the concept phase, a frequency-planning tool enables fine tuning of (...)
此參考設計採用雙通道、14 位元解析度 ADC、取樣率高達 3GSPS 的 ADC32RF45。最大訊號頻寬由 ADC 取樣率除以二得出。在此參考設計中，訊號頻寬超過 1GHz。最大輸入頻率按照 ADC 和輸入變壓器輸入緩衝器的輸入頻寬設定。此參考設計可直接擷取高達 4GHz 的 RF 訊號，適用於所有重要電信頻帶和 S (...)
此參考設計展示 ADC32RF80 雙通道、14 位元、3-GSPS RF 取樣電信接收器。此裝置每個通道包含兩個數位降頻轉換器 (DDC)。DDC 提供 8 到 32 的抽取值，並包含 16 位元數值控制。利用 ADC32RF80 的高取樣率，參考設計可擷取到大量 RF 頻譜，其中包含多頻帶的訊號和潛在的不良干擾。DDC (...)
| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| VQFNP (RMP) | 72 | Ultra Librarian |
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