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數據轉換器
類比轉數位轉換器 (ADC)
高速 ADC (≥10 MSPS)

ADS62P25

現行

雙通道、12 位元、125-MSPS 類比轉數位轉換器 (ADC)

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產品規格表
使用指南

ADS62P25

現行
產品規格表 立即訂購

產品詳細資料

Sample rate (max) (Msps) 125 Resolution (Bits) 12 Number of input channels 2 Interface type DDR LVDS, Parallel CMOS Analog input BW (MHz) 450 Features High Performance Rating Catalog Peak-to-peak input voltage range (V) 2 Power consumption (typ) (mW) 792 Architecture Pipeline SNR (dB) 71.3 ENOB (Bits) 11.4 SFDR (dB) 88 Operating temperature range (°C) -40 to 85 Input buffer No
Sample rate (max) (Msps) 125 Resolution (Bits) 12 Number of input channels 2 Interface type DDR LVDS, Parallel CMOS Analog input BW (MHz) 450 Features High Performance Rating Catalog Peak-to-peak input voltage range (V) 2 Power consumption (typ) (mW) 792 Architecture Pipeline SNR (dB) 71.3 ENOB (Bits) 11.4 SFDR (dB) 88 Operating temperature range (°C) -40 to 85 Input buffer No
VQFN (RGC) 64 81 mm² (9 mm × 9 mm)
  • Maximum Sample Rate: 125 MSPS
  • 12-Bit Resolution with No Missing Codes
  • 95 dB Crosstalk
  • Parallel CMOS and DDR LVDS Output Options
  • 3.5 dB Coarse Gain and Programmable Fine Gain
    up to 6 dB for SNR/SFDR Trade-Off
  • Digital Processing Block with:
    • Offset Correction
    • Fine Gain Correction, in Steps of 0.05 dB
    • Decimation by 2/4/8
    • Built-in and Custom Programmable
      24-Tap Low-/High-/Band-Pass Filters
  • Supports Sine, LVPECL, LVDS, and LVCMOS Clocks and
    Amplitude Down to 400 mVPP
  • Clock Duty Cycle Stabilizer
  • Internal Reference; Supports External Reference also
  • 64-QFN Package (9mm × 9mm)
  • Pin Compatible 14-Bit Family (ADS62P4X)
  • Maximum Sample Rate: 125 MSPS
  • 12-Bit Resolution with No Missing Codes
  • 95 dB Crosstalk
  • Parallel CMOS and DDR LVDS Output Options
  • 3.5 dB Coarse Gain and Programmable Fine Gain
    up to 6 dB for SNR/SFDR Trade-Off
  • Digital Processing Block with:
    • Offset Correction
    • Fine Gain Correction, in Steps of 0.05 dB
    • Decimation by 2/4/8
    • Built-in and Custom Programmable
      24-Tap Low-/High-/Band-Pass Filters
  • Supports Sine, LVPECL, LVDS, and LVCMOS Clocks and
    Amplitude Down to 400 mVPP
  • Clock Duty Cycle Stabilizer
  • Internal Reference; Supports External Reference also
  • 64-QFN Package (9mm × 9mm)
  • Pin Compatible 14-Bit Family (ADS62P4X)

ADS62P2X is a dual channel 12-bit A/D converter family with maximum sample rates up to 125 MSPS. It combines high performance and low power consumption in a compact 64 QFN package. Using an internal sample and hold and low jitter clock buffer, the ADC supports high SNR and high SFDR at high input frequencies. It has coarse and fine gain options that can be used to improve SFDR performance at lower full-scale input ranges.

ADS62P2X includes a digital processing block that consists of several useful and commonly used digital functions such as ADC offset correction, fine gain correction (in steps of 0.05 dB), decimation by 2,4,8 and in-built and custom programmable filters. By default, the digital processing block is bypassed, and its functions are disabled.

Two output interface options exist – parallel CMOS and DDR LVDS (Double Data Rate). ADS62P2X includes internal references while traditional reference pins and associated decoupling capacitors have been eliminated. Nevertheless, the device can also be driven with an external reference. The device is specified over the industrial temperature range (–40°C to 85°C).

ADS62P2X is a dual channel 12-bit A/D converter family with maximum sample rates up to 125 MSPS. It combines high performance and low power consumption in a compact 64 QFN package. Using an internal sample and hold and low jitter clock buffer, the ADC supports high SNR and high SFDR at high input frequencies. It has coarse and fine gain options that can be used to improve SFDR performance at lower full-scale input ranges.

ADS62P2X includes a digital processing block that consists of several useful and commonly used digital functions such as ADC offset correction, fine gain correction (in steps of 0.05 dB), decimation by 2,4,8 and in-built and custom programmable filters. By default, the digital processing block is bypassed, and its functions are disabled.

Two output interface options exist – parallel CMOS and DDR LVDS (Double Data Rate). ADS62P2X includes internal references while traditional reference pins and associated decoupling capacitors have been eliminated. Nevertheless, the device can also be driven with an external reference. The device is specified over the industrial temperature range (–40°C to 85°C).
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技術文件

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重要文件 類型 標題 格式選項 下載最新的英文版本 日期
* 資料表 Dual Channel, 12Bit, 125/105/80/65 MSPS ADC with DDR LVDS/CMOS Outputs datasheet (Rev. C) 2011/5/11
* 使用指南 Interfacing Altera FPGAs to ADS4249 and DAC3482 (TIDA-00069 Reference Guide) 2012/7/10
應用說明 Design Considerations for Avoiding Timing Errors during High-Speed ADC, LVDS Dat (Rev. A) 2015/5/22
應用說明 Why Use Oversampling when Undersampling Can Do the Job? (Rev. A) 2013/7/19
使用指南 TSW4200 Demonstration Kit User's Guide (Rev. C) 2012/10/31
應用說明 Band-Pass Filter Design Techniques for High-Speed ADCs 2012/2/27
應用說明 Driving High-Speed ADCs: Circuit Topologies and System-Level Parameters (Rev. A) 2010/9/10
應用說明 Smart Selection of ADC/DAC Enables Better Design of Software-Defined Radio 2009/4/28
使用指南 ADS62PxxEVM Quick Start Guide (Rev C Board) (Rev. A) 2009/4/2
應用說明 CDCE62005 as Clock Solution for High-Speed ADCs 2008/9/4
應用說明 CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital Converters 2008/6/8
應用說明 Phase Noise Performance and Jitter Cleaning Ability of CDCE72010 2008/6/2
應用說明 QFN Layout Guidelines 2006/7/28

設計與開發

如需其他條款或必要資源，請按一下下方的任何標題以檢視詳細頁面 (如有)。

開發模組 (EVM) 的 GUI

DATACONVERTERPRO-SW — 高速資料轉換器 Pro GUI 安裝程式，v5.31

這款高速資料轉換器專業 GUI 是一款 PC（與 Windows® XP/7/10 相容）程式，旨在協助評估大多數 TI 高速資料轉換器 [類比轉數位轉換器 (ADC) 和數位轉類比轉換器 (DAC)] 和類比前端 (AFE) 平台。DATACONVERTERPRO-SW 旨在支援整個 TSW14xxx 系列資料擷取和模式產生卡，為時域和頻域中的資料轉換器分析提供強大且快速的解決方案，並支援單音、多音和調變訊號。此 GUI 也與 TI 模式產生 GUI 相容，可快速合成單音、多音和調變訊號。

使用者可以向 DATACONVERTERPRO-SW 提供自訂模式，以載入到 TI DAC。支援從 (...)

支援產品和硬體
支援軟體

HSADC-SPI-UTILITY — ADS5400 EVM GUI

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模擬型號

ADS62Pxx Family TINA-TI Transient Reference Design

SBAM008.ZIP (6 KB) - TINA-TI 參考設計
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模擬型號

ADS62Pxx Family TINA-TI Transient Spice Model

SBAM007.TSM (14 KB) - TINA-TI Spice 模型
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模擬型號

ADS62Pxx IBIS Model (Rev. A)

SLAC176 (288 KB) - IBIS 模型
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計算工具

ADC-HARMONIC-CALC — ADC Frequency Calculator Download

    The ADC Harmonic Calculation tool is an excel based calculator for determining the location in frequency space of high order harmonics following Nyquist aliasing in an analog to digital converter.

    Given an ADC sample rate and the span of a signal of interest the calcultor will determine if the 2nd (...)

支援產品和硬體
計算工具

ANALOG-ENGINEER-CALC — PC software analog engineer's calculator

類比工程師的計算機旨在加速類比電路設計工程師定期使用的許多重複計算。此基於 PC 的工具提供圖形介面，列出各種常見計算，從使用回饋電阻器設定運算放大器增益到選擇適當的電路設計元件以穩定類比數位轉換器 (ADC) 驅動緩衝電路。

除了作為獨立工具使用外，此計算機還與類比工程師口袋參考中描述的概念相得益彰。

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設計工具

SBAC119 — TIGAR (Texas Instruments Graphical Evaluation of ADC Response Tool)

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封裝 針腳 CAD 符號、佔位空間與 3D 模型
VQFN (RGC) 64 Ultra Librarian
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