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放大器
運算放大器 (op amps)
精密運算放大器 (Vos < 1mV)

OPA828

現行

高速 (45 MHz 和 150 V/μs)、36-V、低雜訊 (4 nV/√Hz) RRO JFET 運算放大器

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產品規格表

OPA828

現行
產品規格表 立即訂購

產品詳細資料

Number of channels 1 Total supply voltage (+5 V = 5, ±5 V = 10) (max) (V) 36 Total supply voltage (+5 V = 5, ±5 V = 10) (min) (V) 8 Vos (offset voltage at 25°C) (max) (mV) 0.125 Offset drift (typ) (µV/°C) 0.3 Input bias current (max) (pA) 8 GBW (typ) (MHz) 45 Features MUX Friendly Slew rate (typ) (V/µs) 150 Rail-to-rail Out Iq per channel (typ) (mA) 5.5 Vn at 1 kHz (typ) (nV√Hz) 4 CMRR (typ) (dB) 115 Rating Catalog Operating temperature range (°C) -40 to 125 Iout (typ) (A) 0.03 Architecture FET Input common mode headroom (to negative supply) (typ) (V) 2.5 Input common mode headroom (to positive supply) (typ) (V) -3.5 Output swing headroom (to negative supply) (typ) (V) 0.9 Output swing headroom (to positive supply) (typ) (V) -0.9 THD + N at 1 kHz (typ) (%) 0.000028
Number of channels 1 Total supply voltage (+5 V = 5, ±5 V = 10) (max) (V) 36 Total supply voltage (+5 V = 5, ±5 V = 10) (min) (V) 8 Vos (offset voltage at 25°C) (max) (mV) 0.125 Offset drift (typ) (µV/°C) 0.3 Input bias current (max) (pA) 8 GBW (typ) (MHz) 45 Features MUX Friendly Slew rate (typ) (V/µs) 150 Rail-to-rail Out Iq per channel (typ) (mA) 5.5 Vn at 1 kHz (typ) (nV√Hz) 4 CMRR (typ) (dB) 115 Rating Catalog Operating temperature range (°C) -40 to 125 Iout (typ) (A) 0.03 Architecture FET Input common mode headroom (to negative supply) (typ) (V) 2.5 Input common mode headroom (to positive supply) (typ) (V) -3.5 Output swing headroom (to negative supply) (typ) (V) 0.9 Output swing headroom (to positive supply) (typ) (V) -0.9 THD + N at 1 kHz (typ) (%) 0.000028
HVSSOP (DGN) 8 14.7 mm² (3 mm × 4.9 mm) SOIC (D) 8 29.4 mm² (4.9 mm × 6 mm)
  • Low input voltage noise density: 4 nV/√Hz at 1 kHz
  • Input voltage noise: 0.1 Hz to 10 Hz: 60 nVRMS
  • Low input bias current:
    • 0.1 pA (DGN)
    • 1 pA (D)
  • Input offset voltage:
    • 25 µV (DGN)
    • 50 µV (D)
  • Input offset drift:
    • 0.2 µV/°C (DGN)
    • 0.45 µV/°C (D)
  • MUX-friendly inputs
  • Gain bandwidth: 45 MHz
  • Slew rate: 150 V/µs
  • 14-bit settling time: 120 ns
  • Overload power limiter
  • Wide supply voltage range: ±4 V to ±18 V
  • Packages:
    • D Package: 8-pin SOIC
    • DGN Package: 8-pin HVSSOP
  • Low input voltage noise density: 4 nV/√Hz at 1 kHz
  • Input voltage noise: 0.1 Hz to 10 Hz: 60 nVRMS
  • Low input bias current:
    • 0.1 pA (DGN)
    • 1 pA (D)
  • Input offset voltage:
    • 25 µV (DGN)
    • 50 µV (D)
  • Input offset drift:
    • 0.2 µV/°C (DGN)
    • 0.45 µV/°C (D)
  • MUX-friendly inputs
  • Gain bandwidth: 45 MHz
  • Slew rate: 150 V/µs
  • 14-bit settling time: 120 ns
  • Overload power limiter
  • Wide supply voltage range: ±4 V to ±18 V
  • Packages:
    • D Package: 8-pin SOIC
    • DGN Package: 8-pin HVSSOP

The OPA828 and OPA2828 ( OPAx828) JFET input operational amplifiers are the next generation OPA627 and OPA827, combining high speed with high dc precision and ac performance. These op amps supply low offset voltage, low drift over temperature, low bias current, and low noise with only 60-nVRMS 0.1-Hz to 10-Hz noise. The OPAx828 operate over a wide supply-voltage range of ±4 V to ±18 V and a supply current of 5.5 mA/channel, typical.

AC characteristics, including a 45-MHz gain bandwidth product (GBW), a slew rate of 150 V/µs, and precision dc characteristics, make the OPAx828 family an excellent choice for a variety of systems. These include high-speed and high-resolution data-acquisition systems, such as 16-bit to 18-bit mixed signal systems, transimpedance (I/V-conversion) amplifiers, filters, precision ±10-V front ends, and high-impedance sensor-interface applications.

The OPAx828 are available in an 8-pin SOIC package and a thermally enhanced, 8-pin HVSSOP PowerPAD™ integrated circuit package.

The OPA828 and OPA2828 ( OPAx828) JFET input operational amplifiers are the next generation OPA627 and OPA827, combining high speed with high dc precision and ac performance. These op amps supply low offset voltage, low drift over temperature, low bias current, and low noise with only 60-nVRMS 0.1-Hz to 10-Hz noise. The OPAx828 operate over a wide supply-voltage range of ±4 V to ±18 V and a supply current of 5.5 mA/channel, typical.

AC characteristics, including a 45-MHz gain bandwidth product (GBW), a slew rate of 150 V/µs, and precision dc characteristics, make the OPAx828 family an excellent choice for a variety of systems. These include high-speed and high-resolution data-acquisition systems, such as 16-bit to 18-bit mixed signal systems, transimpedance (I/V-conversion) amplifiers, filters, precision ±10-V front ends, and high-impedance sensor-interface applications.

The OPAx828 are available in an 8-pin SOIC package and a thermally enhanced, 8-pin HVSSOP PowerPAD™ integrated circuit package.
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技術文件

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重要文件 類型 標題 格式選項 下載最新的英文版本 日期
* 資料表 OPAx828 Low-Offset, Low-Drift, Low-Noise, 45-MHz, 36-V, JFET-Input Operational Amplifiers datasheet (Rev. D) PDF | HTML 2022/12/29
Circuit design DAC force and sense reference drive circuit (Rev. A) PDF | HTML 2024/9/20
Circuit design Circuit for protecting low-voltage SAR ADC from electrical overstress with minim (Rev. A) PDF | HTML 2024/9/19
白皮書 Op Amp Input and Output Swing Limitations PDF | HTML 2023/12/7
Application brief MUX-Friendly, Precision Operational Amplifiers (Rev. C) PDF | HTML 2022/2/8
Application brief Trade-offs Between CMOS, JFET, and Bipolar Input Stage Technology 2019/5/29
Application brief Simplify Transimpedance Applications with High-bandwidth, Precision JFET Op Amps 2019/5/21
Application brief Green-Williams-Lis: Improved Op Amp Spice Model 2019/1/28

設計與開發

如需其他條款或必要資源，請按一下下方的任何標題以檢視詳細頁面 (如有)。

開發板

AMP-PDK-EVM — 放大器性能開發套件評估模組

放大器性能開發套件 (PDK) 是一款評估模組 (EVM) 套件，可測試通用運算放大器 (op amp) 參數，並與大多數運算放大器和比較器相容。EVM 套件提供主板和多個插槽式子卡選項，可滿足封裝需求，使工程師能夠快速評估和驗證裝置性能。

AMP-PDK-EVM 套件支援五種最熱門的業界標準封裝，包括：

  • D (SOIC-8 和 SOIC-14)
  • PW (TSSOP-14)
  • DGK (VSSOP-8)
  • DBV (SOT23-5 和 SOT23-6)
  • DCK (SC70-5 和 SC70-6)
使用指南: PDF | HTML
支援產品和硬體
模擬型號

PSpice Simulation Companion for DAC Force And Sense Reference Drive Circuit

SBOMBX7.ZIP (101 KB) - PSpice 模型
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模擬型號

OPAx828 PSpice Model (Rev. D)

SBOMAJ0D.ZIP (27 KB) - PSpice 模型
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模擬型號

OPAx828 TINA-TI Reference Design (Rev. C)

SBOMAI8C (300 KB) - TINA-TI 參考設計
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模擬型號

OPAx828 TINA-TI SPICE Model (Rev. C)

SBOMAI9C.ZIP (10 KB) - TINA-TI Spice 模型
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模擬型號

TINA-TI Simulation Companion for DAC Force And Sense Reference Drive Circuit (Rev. A)

SBAM412A.ZIP (69 KB) - TINA-TI 參考設計
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計算工具

ANALOG-ENGINEER-CALC — PC software analog engineer's calculator

類比工程師的計算機旨在加速類比電路設計工程師定期使用的許多重複計算。此基於 PC 的工具提供圖形介面，列出各種常見計算，從使用回饋電阻器設定運算放大器增益到選擇適當的電路設計元件以穩定類比數位轉換器 (ADC) 驅動緩衝電路。

除了作為獨立工具使用外，此計算機還與類比工程師口袋參考中描述的概念相得益彰。

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計算工具

OPAMP-NOISECALC — Noise Calculator

This folder contains three tools to help in understandning and managing noise in cicuits. The included tools are:

  • A noise generator tool - This is a Lab View 4-Run Time executable that generates Gaussian white noise, uniform white noise, 1/f noise, short noise, and 60Hz line noise. Temporal data, (...)
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參考設計

TIDA-010970 — 低雜訊、高線性數位萬用表及資料擷取訊號鏈參考設計

此設計的目標應用包括需要超高精密度以測量 DC 訊號的數位萬用表 (DMM)。此設計採用 ADS127L21B，這是一款高性能 24 位元類比數位轉換器 (ADC)，具有良好的線性度，進而實現了有效的 DC 準確度。REF81 是一款超低漂移埋入式稽納參考二極體，用於校準訊號鏈，以消除增益和偏移誤差。

支援產品和硬體
封裝 針腳 CAD 符號、佔位空間與 3D 模型
HVSSOP (DGN) 8 Ultra Librarian
SOIC (D) 8 Ultra Librarian
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