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運算放大器 (op amps)
高速運算放大器 (GBW ≥ 50 MHz)

OPA2626

現行

高頻寬、高精度、低 THD+N、16 位元和 18 位元 ADC 驅動器

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OPA2626

現行
產品規格表 立即訂購

產品詳細資料

Architecture Voltage FB Number of channels 2 Total supply voltage (+5 V = 5, ±5 V = 10) (min) (V) 2.7 Total supply voltage (+5 V = 5, ±5 V = 10) (max) (V) 5.5 GBW (typ) (MHz) 120 BW at Acl (MHz) 120 Acl, min spec gain (V/V) 1 Slew rate (typ) (V/µs) 115 Vn at flatband (typ) (nV√Hz) 2.5 Vn at 1 kHz (typ) (nV√Hz) 3.2 Iq per channel (typ) (mA) 2 Vos (offset voltage at 25°C) (max) (mV) 0.1 Rail-to-rail In to V-, Out Rating Catalog Operating temperature range (°C) -40 to 125 CMRR (typ) (dB) 117 Input bias current (max) (pA) 4000000 Offset drift (typ) (µV/°C) 0.5 Iout (typ) (mA) 100 2nd harmonic (dBc) 155 3rd harmonic (dBc) 144 Frequency of harmonic distortion measurement (MHz) 0.01
Architecture Voltage FB Number of channels 2 Total supply voltage (+5 V = 5, ±5 V = 10) (min) (V) 2.7 Total supply voltage (+5 V = 5, ±5 V = 10) (max) (V) 5.5 GBW (typ) (MHz) 120 BW at Acl (MHz) 120 Acl, min spec gain (V/V) 1 Slew rate (typ) (V/µs) 115 Vn at flatband (typ) (nV√Hz) 2.5 Vn at 1 kHz (typ) (nV√Hz) 3.2 Iq per channel (typ) (mA) 2 Vos (offset voltage at 25°C) (max) (mV) 0.1 Rail-to-rail In to V-, Out Rating Catalog Operating temperature range (°C) -40 to 125 CMRR (typ) (dB) 117 Input bias current (max) (pA) 4000000 Offset drift (typ) (µV/°C) 0.5 Iout (typ) (mA) 100 2nd harmonic (dBc) 155 3rd harmonic (dBc) 144 Frequency of harmonic distortion measurement (MHz) 0.01
VSSOP (DGK) 8 14.7 mm² 3 x 4.9
  • Excellent dynamic performance:
    • Low distortion: –122 dBc for HD2 and
      –140 dBc for HD3 at 100 kHz
    • Gain bandwidth (G = 100): 120 MHz
    • Slew rate: 115 V/µs
    • 16-bit settling at 4-V step: 280 ns
    • Low voltage noise: 2.5 nV/√Hz at 10 kHz
    • Low output impedance: 1 Ω at 1 MHz
  • Excellent DC precision:
    • Offset voltage: ±100 µV (maximum)
    • Offset voltage drift: ±3 µV/ºC (maximum)
    • Low quiescent current: 2 mA (typical)
  • Input common-mode range includes negative rail
  • Rail-to-rail output
  • Wide temperature range: fully specified from –40°C to +125°C
  • Excellent dynamic performance:
    • Low distortion: –122 dBc for HD2 and
      –140 dBc for HD3 at 100 kHz
    • Gain bandwidth (G = 100): 120 MHz
    • Slew rate: 115 V/µs
    • 16-bit settling at 4-V step: 280 ns
    • Low voltage noise: 2.5 nV/√Hz at 10 kHz
    • Low output impedance: 1 Ω at 1 MHz
  • Excellent DC precision:
    • Offset voltage: ±100 µV (maximum)
    • Offset voltage drift: ±3 µV/ºC (maximum)
    • Low quiescent current: 2 mA (typical)
  • Input common-mode range includes negative rail
  • Rail-to-rail output
  • Wide temperature range: fully specified from –40°C to +125°C

The OPA2626 operational amplifier is a 16-bit and 18-bit, high-precision, successive-approximation register (SAR) analog-to-digital converter (ADC) driver with low total harmonic distortion (THD) and noise. This op amp is fully characterized and specified with a 16-bit settling time of 280 ns that enables a true 16-bit effective number of bits (ENOB). With a high DC precision of only 100-µV offset voltage, a wide gain-bandwidth product of 120 MHz, and a low wideband noise of 2.5 nV/√Hz, this device is optimized for driving high-throughput, high-resolution SAR ADCs in applications such as the ADS88xx family of SAR ADCs.

The OPA2626 is available in an 8-pin VSSOP package and is specified for operation from –40°C to +125°C.

The OPA2626 operational amplifier is a 16-bit and 18-bit, high-precision, successive-approximation register (SAR) analog-to-digital converter (ADC) driver with low total harmonic distortion (THD) and noise. This op amp is fully characterized and specified with a 16-bit settling time of 280 ns that enables a true 16-bit effective number of bits (ENOB). With a high DC precision of only 100-µV offset voltage, a wide gain-bandwidth product of 120 MHz, and a low wideband noise of 2.5 nV/√Hz, this device is optimized for driving high-throughput, high-resolution SAR ADCs in applications such as the ADS88xx family of SAR ADCs.

The OPA2626 is available in an 8-pin VSSOP package and is specified for operation from –40°C to +125°C.
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重要文件 類型 標題 格式選項 日期
* Data sheet OPA2626 High-Speed, High-Precision, Low-Distortion, 16-Bit and 18-Bit Analog-to-Digital Converter (ADC) Driver datasheet (Rev. A) PDF | HTML 2019年 12月 19日
E-book The Signal e-book: A compendium of blog posts on op amp design topics 2017年 3月 28日

設計與開發

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模擬型號

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OPA626 TINA-TI Spice Model

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計算工具

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The analog engineer’s calculator is designed to speed up many of the repetitive calculations that analog circuit design engineers use on a regular basis. This PC-based tool provides a graphical interface with a list of various common calculations ranging from setting operational-amplifier (...)

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PSPICE-FOR-TI — PSpice® for TI 設計與模擬工具

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PSpice for TI 設計和模擬環境可讓您使用其內建函式庫來模擬複雜的混合訊號設計。在進行佈局和製造之前，建立完整的終端設備設計和解決方案原型，進而縮短上市時間並降低開發成本。 

在 PSpice for TI 設計與模擬工具中，您可以搜尋 TI (...)
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TINA-TI — 基於 SPICE 的類比模擬程式

TINA-TI provides all the conventional DC, transient and frequency domain analysis of SPICE and much more. TINA has extensive post-processing capability that allows you to format results the way you want them. Virtual instruments allow you to select input waveforms and probe circuit nodes voltages (...)
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參考設計

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此參考設計在打造時將電子影像系統納入考量。現今的影像感測器對 ADC 有高要求，包括：優異的線性度（DNL < 0.5 LSB 與 INL < 4 LSB）、高解析度（12 至 18 位元）、高速（高達 20MSPS）和高信噪比（SNR > 74dB），可確保優異的影像品質，並避免隨時間產生的失真問題。此參考設計有 TI 的低雜訊、高速放大器、全差動放大器 (FDA)、高速 ADC 和低雜訊 LDO，展示如何設計高性能類比訊號鏈，將熱成像攝影機中的像素輸出訊號數位化。
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VSSOP (DGK) 8 Ultra Librarian
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