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數據轉換器
類比轉數位轉換器 (ADC)
高速 ADC (≥10 MSPS)

ADC3642

現行

雙通道 14 位元 25 MSPS 低雜訊、超低功耗類比轉數位轉換器 (ADC)

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產品規格表

ADC3642

現行
產品規格表 立即訂購

產品詳細資料

Sample rate (max) (Msps) 25 Resolution (Bits) 14 Number of input channels 2 Interface type CMOS Analog input BW (MHz) 900 Features High Dynamic Range, Low Power Rating Catalog Peak-to-peak input voltage range (V) 2.25 Power consumption (typ) (mW) 35 Architecture SAR SNR (dB) 79 ENOB (Bits) 12.8 SFDR (dB) 95 Operating temperature range (°C) -40 to 105 Input buffer No
Sample rate (max) (Msps) 25 Resolution (Bits) 14 Number of input channels 2 Interface type CMOS Analog input BW (MHz) 900 Features High Dynamic Range, Low Power Rating Catalog Peak-to-peak input voltage range (V) 2.25 Power consumption (typ) (mW) 35 Architecture SAR SNR (dB) 79 ENOB (Bits) 12.8 SFDR (dB) 95 Operating temperature range (°C) -40 to 105 Input buffer No
WQFN (RSB) 40 25 mm² 5 x 5
  • Dual channel
  • 14-bit 10/25/65 MSPS ADC
  • Noise floor: –155 dBFS/Hz
  • Ultra-low power with optimized power scaling: 29 mW/ch (10 MSPS) to 72 mW/ch (65 MSPS)
  • Latency: 1 clock cycle
  • 14-Bit, no missing codes
  • INL: ±0.6 LSB; DNL: ±0.2 LSB
  • Reference: external or internal
  • Industrial temperature range: –40°C to +105°C
  • On-chip digital filter (optional)
    • Decimation by 2, 4, 8, 16, 32
    • 32-bit NCO
  • DDR and Serial CMOS interface
  • Small footprint: 40-VQFN (5 mm × 5 mm) package
  • Single 1.8-V supply
  • Spectral performance (fIN = 5 MHz):
    • SNR: 79.0 dBFS
    • SFDR: 93-dBc HD2, HD3
    • SFDR: 101-dBFS worst spur
  • Spectral performance (fIN = 64 MHz):
    • SNR: 74.0 dBFS
    • SFDR: 84-dBc HD2, HD3
    • SFDR: 90-dBFS worst spur
  • Dual channel
  • 14-bit 10/25/65 MSPS ADC
  • Noise floor: –155 dBFS/Hz
  • Ultra-low power with optimized power scaling: 29 mW/ch (10 MSPS) to 72 mW/ch (65 MSPS)
  • Latency: 1 clock cycle
  • 14-Bit, no missing codes
  • INL: ±0.6 LSB; DNL: ±0.2 LSB
  • Reference: external or internal
  • Industrial temperature range: –40°C to +105°C
  • On-chip digital filter (optional)
    • Decimation by 2, 4, 8, 16, 32
    • 32-bit NCO
  • DDR and Serial CMOS interface
  • Small footprint: 40-VQFN (5 mm × 5 mm) package
  • Single 1.8-V supply
  • Spectral performance (fIN = 5 MHz):
    • SNR: 79.0 dBFS
    • SFDR: 93-dBc HD2, HD3
    • SFDR: 101-dBFS worst spur
  • Spectral performance (fIN = 64 MHz):
    • SNR: 74.0 dBFS
    • SFDR: 84-dBc HD2, HD3
    • SFDR: 90-dBFS worst spur

The ADC364x family of devices are low-noise, ultra-low power, 14-bit, 10-MSPS to 65-MSPS dual-channel, high-speed analog-to-digital converters (ADCs). Designed for low power consumption, these devices deliver a noise spectral density of –155 dBFS/Hz, combined with excellent linearity and dynamic range. The ADC364x offers very good dc precision, together with IF sampling support, which make the device an excellent choice for a wide range of applications. High-speed control loops benefit from the short latency of only one clock cycle. The ADC consumes only 72 mW/ch at 65 MSPS, and power consumption scales well with lower sampling rates.

The ADC364x use a DDR or serial CMOS interface to output the data offering lowest power digital interface, together with flexibility to minimize the number of digital interconnects. These devices are a pin-to-pin compatible family with different speed grades. These devices support the extended industrial temperature range of –40 to +105⁰C.

The ADC364x family of devices are low-noise, ultra-low power, 14-bit, 10-MSPS to 65-MSPS dual-channel, high-speed analog-to-digital converters (ADCs). Designed for low power consumption, these devices deliver a noise spectral density of –155 dBFS/Hz, combined with excellent linearity and dynamic range. The ADC364x offers very good dc precision, together with IF sampling support, which make the device an excellent choice for a wide range of applications. High-speed control loops benefit from the short latency of only one clock cycle. The ADC consumes only 72 mW/ch at 65 MSPS, and power consumption scales well with lower sampling rates.

The ADC364x use a DDR or serial CMOS interface to output the data offering lowest power digital interface, together with flexibility to minimize the number of digital interconnects. These devices are a pin-to-pin compatible family with different speed grades. These devices support the extended industrial temperature range of –40 to +105⁰C.
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我們的 ADC3660 系列贏得 2021 年世界電子產品成就獎 (WEAA) 放大器/資料轉換類別的年度最佳產品。

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重要文件 類型 標題 格式選項 日期
* Data sheet ADC364x 14-bit, 10-MSPS to 65-MSPS, Low-Noise, Low Power Dual Channel ADC datasheet (Rev. A) PDF | HTML 2022年 5月 20日
Application note Practical Clocking Considerations That Give Your Next High-Speed Converter Design an Edge (Rev. A) PDF | HTML 2025年 4月 11日
Application note High-Speed ADC: How to Properly Terminate Single-ended CMOS Digital Outputs 2020年 12月 9日
Application note High Speed SAR ADC: Data Rate, Performance, and Pin Count Optimization PDF | HTML 2020年 12月 8日
Analog Design Journal How to simplify AFE filtering via high‐speed ADCs with internal digital filters 2020年 1月 10日

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This high-speed data converter pro GUI is a PC (Windows® XP/7/10 compatible) program designed to aid in evaluation of most TI high-speed data converter [analog-to-digital converter (ADC) and digital-to-analog converter (DAC)] and analog front-end (AFE) platforms. Designed to support the entire (...)

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