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數據轉換器
類比轉數位轉換器 (ADC)
高速 ADC (≥10 MSPS)

ADC12J4000

現行

12 位元、4.0-GSPS、RF 取樣類比轉數位轉換器 (ADC)

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產品規格表

ADC12J4000

現行
產品規格表 立即訂購

產品詳細資料

Sample rate (max) (Msps) 4000 Resolution (Bits) 12 Number of input channels 1 Interface type JESD204B Analog input BW (MHz) 3200 Features Ultra High Speed Rating Catalog Peak-to-peak input voltage range (V) 0.725 Power consumption (typ) (mW) 2000 Architecture Folding Interpolating SNR (dB) 55 ENOB (Bits) 8.8 SFDR (dB) 71 Operating temperature range (°C) -40 to 85 Input buffer Yes
Sample rate (max) (Msps) 4000 Resolution (Bits) 12 Number of input channels 1 Interface type JESD204B Analog input BW (MHz) 3200 Features Ultra High Speed Rating Catalog Peak-to-peak input voltage range (V) 0.725 Power consumption (typ) (mW) 2000 Architecture Folding Interpolating SNR (dB) 55 ENOB (Bits) 8.8 SFDR (dB) 71 Operating temperature range (°C) -40 to 85 Input buffer Yes
VQFNP (NKE) 68 100 mm² 10 x 10
  • Excellent Noise and Linearity up to and beyond FIN = 3 GHz
  • Configurable DDC
  • Decimation Factors from 4 to 32 (Complex Baseband Out)
  • Usable Output Bandwidth of 800 MHz at
    4x Decimation and 4000 MSPS
  • Usable Output Bandwidth of 100 MHz at
    32x Decimation and 4000 MSPS
  • Bypass Mode for Full Nyquist Output Bandwidth
  • Low Pin-Count JESD204B Subclass 1 Interface
  • Automatically Optimized Output Lane Count
  • Embedded Low Latency Signal Range Indication
  • Low Power Consumption
  • Key Specifications:
    • Max Sampling Rate: 4000 MSPS
    • Min Sampling Rate: 1000 MSPS
    • DDC Output Word Size: 15-Bit Complex (30 bits total)
    • Bypass Output Word Size: 12-Bit Offset Binary
    • Noise Floor: −149 dBFS/Hz or −150.8 dBm/Hz
    • IMD3: −64 dBc (FIN = 2140 MHz ± 30 MHz at −13 dBFS)
    • FPBW (–3 dB): 3.2 GHz
    • Peak NPR: 46 dB
    • Supply Voltages: 1.9 V and 1.2 V
    • Power Consumption
      • Bypass (4000 MSPS): 2 W
      • Decimate by 10 (4000 MSPS): 2 W
      • Power Down Mode: <50 mW
  • Excellent Noise and Linearity up to and beyond FIN = 3 GHz
  • Configurable DDC
  • Decimation Factors from 4 to 32 (Complex Baseband Out)
  • Usable Output Bandwidth of 800 MHz at
    4x Decimation and 4000 MSPS
  • Usable Output Bandwidth of 100 MHz at
    32x Decimation and 4000 MSPS
  • Bypass Mode for Full Nyquist Output Bandwidth
  • Low Pin-Count JESD204B Subclass 1 Interface
  • Automatically Optimized Output Lane Count
  • Embedded Low Latency Signal Range Indication
  • Low Power Consumption
  • Key Specifications:
    • Max Sampling Rate: 4000 MSPS
    • Min Sampling Rate: 1000 MSPS
    • DDC Output Word Size: 15-Bit Complex (30 bits total)
    • Bypass Output Word Size: 12-Bit Offset Binary
    • Noise Floor: −149 dBFS/Hz or −150.8 dBm/Hz
    • IMD3: −64 dBc (FIN = 2140 MHz ± 30 MHz at −13 dBFS)
    • FPBW (–3 dB): 3.2 GHz
    • Peak NPR: 46 dB
    • Supply Voltages: 1.9 V and 1.2 V
    • Power Consumption
      • Bypass (4000 MSPS): 2 W
      • Decimate by 10 (4000 MSPS): 2 W
      • Power Down Mode: <50 mW

The ADC12J4000 device is a wideband sampling and digital tuning device. Texas Instruments’ giga-sample analog-to-digital converter (ADC) technology enables a large block of frequency spectrum to be sampled directly at RF. An integrated DDC (Digital Down Converter) provides digital filtering and down-conversion. The selected frequency block is made available on a JESD204B serial interface. Data is output as baseband 15-bit complex information for ease of downstream processing. Based on the digital down-converter (DDC) decimation and link output rate settings, this data is output on 1 to 5 lanes of the serial interface.

A DDC bypass mode allows the full rate 12-bit raw ADC data to also be output. This mode of operation requires 8 lanes of serial output.

The ADC12J4000 device is available in a 68-pin VQFN package. The device operates over the Industrial (–40°C ≤ TA ≤ 85°C) ambient temperature range.

The ADC12J4000 device is a wideband sampling and digital tuning device. Texas Instruments’ giga-sample analog-to-digital converter (ADC) technology enables a large block of frequency spectrum to be sampled directly at RF. An integrated DDC (Digital Down Converter) provides digital filtering and down-conversion. The selected frequency block is made available on a JESD204B serial interface. Data is output as baseband 15-bit complex information for ease of downstream processing. Based on the digital down-converter (DDC) decimation and link output rate settings, this data is output on 1 to 5 lanes of the serial interface.

A DDC bypass mode allows the full rate 12-bit raw ADC data to also be output. This mode of operation requires 8 lanes of serial output.

The ADC12J4000 device is available in a 68-pin VQFN package. The device operates over the Industrial (–40°C ≤ TA ≤ 85°C) ambient temperature range.
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技術文件

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重要文件 類型 標題 格式選項 日期
* Data sheet ADC12J4000 12-Bit, 4-GSPS ADC With Integrated DDC datasheet (Rev. D) PDF | HTML 2017年 10月 19日
Technical article How to minimize filter loss when you drive an ADC PDF | HTML 2016年 10月 20日
Application note 66AK2L06 JESD Attach to ADC12J4000/DAC38J84 Getting Started Guide (Rev. B) 2016年 6月 20日
Technical article How to complete your RF sampling solution PDF | HTML 2016年 5月 18日
Technical article RF sampling: clocking is the key every time PDF | HTML 2015年 12月 11日
Technical article Are 66AK2L06 SoCs an answer to miniaturization of test and measurement equipment? PDF | HTML 2015年 12月 2日
Technical article RF sampling: interleaving builds faster ADCs PDF | HTML 2015年 10月 29日
Design guide 66AK2L06 JESD Attach to ADC12J4000 / DAC38J84 Design Guide (Rev. A) 2015年 10月 22日
Application note System solution for avionics & defense 2015年 9月 23日
Technical article RF sampling: digital mixers make mixing fun PDF | HTML 2015年 9月 17日
Technical article RF sampling: How over-sampling is cheating physics PDF | HTML 2015年 8月 21日
Technical article Managing input data rates is a breeze PDF | HTML 2015年 6月 19日
Technical article Why bother with RF sampling? PDF | HTML 2015年 5月 15日
Analog Design Journal Analog Applications Journal 2Q 2015 2015年 4月 28日
Analog Design Journal JESD204B multi-device synchronization: Breaking down the requirements 2015年 4月 28日
White paper Ready to make the jump to JESD204B? White Paper (Rev. B) 2015年 3月 19日

設計與開發

如需其他條款或必要資源，請按一下下方的任何標題以檢視詳細頁面 (如有)。

開發板

ADC12J4000EVM — ADC12J4000 12 位元、4.0 GSPS、射頻取樣類比轉數位轉換器評估模組

ADC12J4000EVM 是一個用於評估 TI 的 ADC12J4000 的評估模組 (EVM)。ADC12J4000 是一款具有緩衝類比輸入的低功耗、12 位元、4-GSPS 射頻取樣類比轉數位轉換器 (ADC)，是具可編程 NCO 和降取設定 (包括未降取的 12 位元 ADC 輸出) 的整合式數位降壓轉換器，並且具有 JESD204B 介面。此 EVM 具有變壓器耦合的類比輸入，可適應廣泛的訊號來源和頻率。EVM 隨附 LMX2581 時鐘合成器和 LMK04828 JESD204B 時鐘產生器，可配置為提供適用於完整 JESD204B 子類別 1 計時解決方案的超低抖動 ADC (...)

使用指南: PDF
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韌體

TI204C-IP — Request for JESD204 rapid design IP

The JESD204 rapid design IP has been designed to enable FPGA engineers to achieve an accelerated path to a working JESD204 system. The IP has been architected in a way that downstream digital processing and other application logic are isolated from most of the performance- and timing-critical (...)

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要求
開發模組 (EVM) 的 GUI

DATACONVERTERPRO-SW — High Speed Data Converter Pro GUI Installer, v5.31

This high-speed data converter pro GUI is a PC (Windows® XP/7/10 compatible) program designed to aid in evaluation of most TI high-speed data converter [analog-to-digital converter (ADC) and digital-to-analog converter (DAC)] and analog front-end (AFE) platforms. Designed to support the entire (...)

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模擬型號

ADC12J1600 IBIS Model (Rev. A)

SLAM223A.ZIP (24 KB) - IBIS Model
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模擬型號

ADC12J4000 IBIS-AMI Model (Rev. A)

SLAM198A.ZIP (4134 KB) - IBIS-AMI Model
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計算工具

FREQ-DDC-FILTER-CALC — RF-Sampling Frequency Planner, Analog Filter, and DDC Excel Calculator

This Excel calculator provides system designers a way to simplify the design and debugging of direct RF-sampling receivers. It offers three functions: frequency planning, analog filtering, and decimation filter spur location.

In the concept phase, a frequency-planning tool enables fine tuning of (...)

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模擬工具

PSPICE-FOR-TI — PSpice® for TI 設計與模擬工具

PSpice® for TI 是有助於評估類比電路功能的設計和模擬環境。這款全功能設計和模擬套件使用 Cadence® 的類比分析引擎。PSpice for TI 包括業界最大的模型庫之一，涵蓋我們的類比和電源產品組合，以及特定類比行為模型，且使用無需支付費用。

PSpice for TI 設計和模擬環境可讓您使用其內建函式庫來模擬複雜的混合訊號設計。在進行佈局和製造之前，建立完整的終端設備設計和解決方案原型，進而縮短上市時間並降低開發成本。 

在 PSpice for TI 設計與模擬工具中，您可以搜尋 TI (...)
要求
參考設計

TIDA-00431 — 採用 8 GHz DC 耦合差動放大器的射頻取樣 4 GSPS ADC 參考設計

Wideband radio frequency (RF) receivers allow greatly increased flexibility in radio designs. The wide instantaneous bandwidth allows flexible tuning without changing hardware and the ability to capture multiple channels at widely separated frequencies.

This reference design describes a wideband RF (...)

Design guide: PDF
電路圖: PDF
參考設計

TIDA-01017 — 適用於示波器、無線測試器和雷達的高速多通道 ADC 時鐘參考設計

TIDA-01017 參考設計展示高速多通道系統時脈解決方案的性能，並透過測量射頻取樣 ADC 整個輸入頻率範圍的通道間偏斜進行分析。通道間偏斜對於相位陣列雷達和示波器應用而言至關重要。ADC12J4000 是一款具緩衝類比輸入的低功率 12 位元 4 GSPS 射頻取樣類比轉數位轉換器 (ADC)，整合式數位降壓轉換器，具備 JESD204B 介面，可擷取高達 4GHz 的訊號。此設計展示了使用 LMK04828 的時脈解決方案，以使用經過同步的 SYSREF 在多個 ADC12J4000 訊號鏈之間實現同步。
Design guide: PDF
電路圖: PDF
參考設計

TIDA-01015 — 適用於數位示波器和無線測試器中的 12 位元高速 ADC 的 4 GHz 時鐘參考設計

TIDA-01015 是一款針對高速直接射頻取樣 GSPS ADC 的時鐘解決方案參考設計。此設計展現了取樣時鐘對於實現第二奈奎斯特區輸入訊號頻率之高 SNR 的重要性。ADC12J4000 是一款 12 位元、4GSPS 的射頻取樣 ADC，具有 3.2GHz 的 3dB 輸入頻寬，可擷取高達 4GHz 的訊號。此設計重點展示採用 TRF3765 的時鐘解決方案，用於 ADC12J4000，可在高輸入頻率下實現優異的 SNR 性能，適用於數位儲存示波器 (DSO) 和無線測試儀等應用。
Design guide: PDF
電路圖: PDF
參考設計

TIDEP0034 — 連接至寬頻 ADC 和 DAC 且具有 JESD204B 的 66AK2L06 DSP+ARM 處理器

For developers currently using an FPGA or ASIC to connect to high speed data converters who need faster time to market with increased performance and significant reduction in cost, power, and size this reference design includes the first widely available processor integrating a JESD204B interface (...)
Design guide: PDF
電路圖: PDF
參考設計

TIDA-00826 — 50 Ohm 2 GHz 示波器前端參考設計

This reference design is part of an analog front-end for 50Ω-input oscilloscope application. System designers can readily use this evaluation platform to process input signals from DC to 2 GHz in both frequency-domain and time-domain applications.
Design guide: PDF
電路圖: PDF
參考設計

TIDA-00467 — 同步多個 JESD204B ADC 以進行發射器位置定位的參考設計

A common technique to estimate the position of emitters uses the amplitude and phase shift data of a signal derived from an array of spatially distributed sensors. For such systems, it is important to guarantee a deterministic phase relationship between the sensors to minimize errors in the actual (...)
Design guide: PDF
電路圖: PDF
參考設計

TIDA-00432 — 使用適用於相位陣列雷達系統的 Xilinx 平台，將 JESD204B Giga-Sample ADC 同步化

This system level design shows how two ADC12J4000 evaluation modules (EVMs) can be synchronized together using a Xilinx VC707 platform. The design document describes the required hardware modifications and device configurations, including the clocking scheme. Example configuration files are shown (...)
Design guide: PDF
電路圖: PDF
參考設計

TIDA-00359 — 適用於 GSPS ADC 的時鐘解決方案參考設計

Low cost, high performance clocking solution for GSPS data converters. This reference design discusses the use of a TRF3765, a low noise frequency synthesizer, generating the sampling clock for a 4 GSPS analog-to-digital converter (ADC12J4000). Experiments demonstrate data sheet comparable SNR and (...)
Design guide: PDF
電路圖: PDF
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VQFNP (NKE) 68 Ultra Librarian
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