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ADS8904B

現行

具有內部 VREF 緩衝器、內部 LDO 和強化型 SPI 的 20 位元、250-kSPS、1 通道 SAR ADC

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產品規格表

ADS8904B

現行
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產品詳細資料

Resolution (Bits) 20 Sample rate (max) (ksps) 250 Number of input channels 1 Interface type Enhanced SPI, SPI Architecture SAR Input type Differential Rating Catalog Reference mode External Input voltage range (max) (V) 5 Input voltage range (min) (V) 0 Features Daisy-Chainable, Oscillator Operating temperature range (°C) -40 to 125 Power consumption (typ) (mW) 14 Analog supply voltage (min) (V) 3 Analog supply voltage (max) (V) 5.5 SNR (dB) 104.5 Digital supply (min) (V) 1.65 Digital supply (max) (V) 5.5
Resolution (Bits) 20 Sample rate (max) (ksps) 250 Number of input channels 1 Interface type Enhanced SPI, SPI Architecture SAR Input type Differential Rating Catalog Reference mode External Input voltage range (max) (V) 5 Input voltage range (min) (V) 0 Features Daisy-Chainable, Oscillator Operating temperature range (°C) -40 to 125 Power consumption (typ) (mW) 14 Analog supply voltage (min) (V) 3 Analog supply voltage (max) (V) 5.5 SNR (dB) 104.5 Digital supply (min) (V) 1.65 Digital supply (max) (V) 5.5
VQFN (RGE) 24 16 mm² (4 mm × 4 mm)
  • Resolution: 20-Bits
  • High Sample Rate With No Latency Output:
    • ADS8900B: 1MSPS
    • ADS8902B: 500kSPS
    • ADS8904B: 250kSPS
  • Integrated LDO Enables Low-Power, Single-Supply Operation
  • Low-Power Reference Buffer With No Droop
  • Excellent AC and DC Performance:
    • SNR: 104.5dB, THD: –125dB
    • DNL: ±0.2ppm, 20 Bit No-Missing-Codes
    • INL: ±1ppm
  • Wide Input Range:
    • Unipolar DifferentialInput Range: ±VREF
    • VREF Input Range: 2.5V to 5V
  • Enhanced-SPI Digital Interface
    • Interface SCLK: 22MHz at 1MSPS
    • Configurable Data Parity Output
  • Extended Temperature Range: –40°C to +125°C
  • Small Footprint: 4mm × 4mm VQFN
  • Resolution: 20-Bits
  • High Sample Rate With No Latency Output:
    • ADS8900B: 1MSPS
    • ADS8902B: 500kSPS
    • ADS8904B: 250kSPS
  • Integrated LDO Enables Low-Power, Single-Supply Operation
  • Low-Power Reference Buffer With No Droop
  • Excellent AC and DC Performance:
    • SNR: 104.5dB, THD: –125dB
    • DNL: ±0.2ppm, 20 Bit No-Missing-Codes
    • INL: ±1ppm
  • Wide Input Range:
    • Unipolar DifferentialInput Range: ±VREF
    • VREF Input Range: 2.5V to 5V
  • Enhanced-SPI Digital Interface
    • Interface SCLK: 22MHz at 1MSPS
    • Configurable Data Parity Output
  • Extended Temperature Range: –40°C to +125°C
  • Small Footprint: 4mm × 4mm VQFN

The ADS8900B, ADS8902B, and ADS8904B (ADS890xB) belong to a family of pin-to-pin compatible, high-speed, single-channel, high-precision, 20-bit successive-approximation-register (SAR) analog-to-digital converters (ADCs) with an integrated reference buffer and integrated low-dropout regulator (LDO). The device family includes the ADS891xB (18-bit) and ADS892xB (16-bit) resolution variants.

The ADS890xB boost analog performance while maintaining high-resolution data transfer by using TI’s enhanced-SPI feature. Enhanced-SPI enables the ADS89xxB to achieve high throughput at lower clock speeds, thereby simplifying the board layout and lowering system cost. Enhanced-SPI also simplifies clocking-in of data, thereby making this device an excellent choice for applications involving FPGAs, DSPs. The ADS89xxB is compatible with a standard SPI Interface.

The ADS890xB has an internal data parity feature that can be appended to the ADC data output. ADC data validation by the host, using parity bits, improves system reliability.

The ADS8900B, ADS8902B, and ADS8904B (ADS890xB) belong to a family of pin-to-pin compatible, high-speed, single-channel, high-precision, 20-bit successive-approximation-register (SAR) analog-to-digital converters (ADCs) with an integrated reference buffer and integrated low-dropout regulator (LDO). The device family includes the ADS891xB (18-bit) and ADS892xB (16-bit) resolution variants.

The ADS890xB boost analog performance while maintaining high-resolution data transfer by using TI’s enhanced-SPI feature. Enhanced-SPI enables the ADS89xxB to achieve high throughput at lower clock speeds, thereby simplifying the board layout and lowering system cost. Enhanced-SPI also simplifies clocking-in of data, thereby making this device an excellent choice for applications involving FPGAs, DSPs. The ADS89xxB is compatible with a standard SPI Interface.

The ADS890xB has an internal data parity feature that can be appended to the ADC data output. ADC data validation by the host, using parity bits, improves system reliability.
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ADS8900B 現行 具有內部 VREF 緩衝器、內部 LDO 和強化型 SPI 的 20 位元、1-MSPS、1 通道 SAR ADC Higher sampling rate (1 MSPS)

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重要文件 類型 標題 格式選項 下載最新的英文版本 日期
* 資料表 ADS890xB 20-Bit, High-Speed SAR ADCs With Integrated Reference Buffer, and Enhanced Performance Features datasheet (Rev. B) PDF | HTML 2026/5/12
應用說明 Attenuator Amplifier Design to Maximize the Input Voltage of Differential ADCs 2018/6/14
Application brief Improving Input Settling for Precision Data Converters 2017/12/12
Application brief Optimizing Data Transfer on High-Resolution, High-Throughput Data Converters 2017/12/12
Application brief Simplify Isolation Designs Using an Enhanced-SPI ADC Interface 2017/12/11
白皮書 Enabling Faster, Smarter, and More Robust Solutions for SAR ADSx With multiSPI 2016/11/8

設計與開發

如需其他條款或必要資源，請按一下下方的任何標題以檢視詳細頁面 (如有)。

開發板

ADS8900BEVM-PDK — ADS8900B 全差動輸入、20 位元 SAR ADC EVM 性能展示套件 (PDK)

ADS8900B 評估模組 (EVM) 和性能展示套件 (PDK) 是評估 ADS8900B 連續近似暫存器 (SAR) 類比轉數位轉換器 (ADC) 效能的平台、這是一款全差動輸入、20 位元、1MSPS 裝置。ADS8900BEVM-PDK 包括 ADS8900B EVM 板和精密主機介面 (PHI) 控制器板，可啟用隨附的電腦軟體。

使用指南: PDF | HTML
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模擬型號

ADS8904B PSpice Model

SBAM484.ZIP (11178 KB) - PSpice 模型
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模擬型號

ADS8904B TINA-TI Reference Design

SBAM306.TSC (7126 KB) - TINA-TI 參考設計
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模擬型號

ADS8904B TINA-TI Spice Model

SBAM307.TSM (26 KB) - TINA-TI Spice 模型
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模擬型號

ADS890XB IBIS Model (Rev. A)

SBAM305A.ZIP (16 KB) - IBIS 模型
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計算工具

ANALOG-ENGINEER-CALC — PC software analog engineer's calculator

類比工程師的計算機旨在加速類比電路設計工程師定期使用的許多重複計算。此基於 PC 的工具提供圖形介面，列出各種常見計算，從使用回饋電阻器設定運算放大器增益到選擇適當的電路設計元件以穩定類比數位轉換器 (ADC) 驅動緩衝電路。

除了作為獨立工具使用外，此計算機還與類比工程師口袋參考中描述的概念相得益彰。

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設計工具

ADC-DAC-TO-VREF-SELECT-DESIGN-TOOL — The ADC-TO-VREF-SELECT tool enables the pairing of TI ADCs, DACs, and series voltage references.

The ADC-TO-VREF-SELECT tool enables the pairing of TI analog-to-digital converters (ADCs) and series voltage references. Users can select an ADC device and the desired reference voltage, and the tool will list up to two voltage reference recommendations.
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參考設計

TIPD211 — 適用於測試與量測應用的 20 位元、1 MSPS、四通道小型設計參考設計

混合訊號 SOC 測試器、記憶體測試器、電池測試器、液晶顯示器 (LCD) 測試器、桌上型設備、高密度數位卡、高密度電源卡、X 光、MRI 等終端設備需要多個快速又可同時取樣的通道，並具備出色的 DC 和 AC 性能，以及低功率和小巧的電路板空間。此設計中建議的解決方案使用高性能 SAR ADC (ADS8910B)、精準放大器 (OPA2625) 以及精準電壓參考 (REF5050)。
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VQFN (RGE) 24 Ultra Librarian
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