The pin-compatible DAC37J82/DAC38J82 family is a very low power, 16-bit, dual-channel, 1.6/2.5 GSPS digital to analog converter (DAC) with JESD204B interface. The maximum input data rate is 1.23 GSPS.
Digital data is input to the device through 1, 2, 4 or 8 configurable serial JESD204B lanes running up to 12.5 Gbps with on-chip termination and programmable equalization. The interface allows JESD204B Subclass 1 SYSREF based deterministic latency and full synchronization of multiple devices.
The device includes features that simplify the design of complex transmit architectures. Fully bypassable 2x to 16x digital interpolation filters with over 90 dB of stop-band attenuation simplify the data interface and reconstruction filters. An on-chip 48-bit Numerically Controlled Oscillator (NCO) and independent complex mixers allow flexible and accurate carrier placement.
A high-performance low jitter PLL simplifies clocking of the device without significant impact on the dynamic range. The digital Quadrature Modulator Correction (QMC) and Group Delay Correction (QDC) enable complete IQ compensation for gain, offset, phase, and group delay between channels in direct up-conversion applications. A programmable Power Amplifier (PA) protection mechanism is available to provide PA protection in cases when the abnormal power behavior of the input data is detected.
DAC37J82/DAC38J82 family provides four analog outputs, and the data from the internal two digital paths can be routed to any two out of these four DAC outputs via the output multiplexer.
| 重要文件 | 類型 | 標題 | 格式選項 | 日期 |
|---|---|---|---|---|
| * | Data sheet | DAC3xJ82 Dual-Channel, 16-Bit, 1.6/2.5 GSPS, Digital-to-Analog Converters with 12.5 Gbps JESD204B Interface datasheet (Rev. B) | PDF | HTML | 2014年 5月 6日 |
| Application note | DAC3xJ8x Device Initialization and SYSREF Configuration | 2017年 9月 27日 | ||
| Application note | System solution for avionics & defense | 2015年 9月 23日 | ||
| White paper | Ready to make the jump to JESD204B? White Paper (Rev. B) | 2015年 3月 19日 | ||
| EVM User's guide | Altera JESD204B IP Core and TI DAC37J84 Hardware Checkout Report (Rev. A) | 2014年 9月 15日 | ||
| Design guide | Analog Interfacing Networks for DAC348x and Modulators (TIDA-00077) (Rev. A) | 2013年 8月 14日 | ||
| Application note | High Speed, Digital-to-Analog Converters Basics (Rev. A) | 2012年 10月 23日 |
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針對此類多天線發射器的實作，每個獨立的發射器都需要數位類比轉換器 (DAC) 來將數位位元轉換為射頻訊號。多個發射器與其相關的天線也必須在時間上同步。此設計可採用 JESD204B (...)
| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| FCCSP (AAV) | 144 | Ultra Librarian |
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