產品詳細資料

Sample rate (max) (Msps) 125 Resolution (Bits) 14 Number of input channels 1 Interface type Parallel CMOS Analog input BW (MHz) 750 Features High Performance Rating HiRel Enhanced Product Peak-to-peak input voltage range (V) 2.3 Power consumption (typ) (mW) 780 Architecture Pipeline SNR (dB) 71.5 ENOB (Bits) 11.3 SFDR (dB) 84 Operating temperature range (°C) -55 to 125 Input buffer No
Sample rate (max) (Msps) 125 Resolution (Bits) 14 Number of input channels 1 Interface type Parallel CMOS Analog input BW (MHz) 750 Features High Performance Rating HiRel Enhanced Product Peak-to-peak input voltage range (V) 2.3 Power consumption (typ) (mW) 780 Architecture Pipeline SNR (dB) 71.5 ENOB (Bits) 11.3 SFDR (dB) 84 Operating temperature range (°C) -55 to 125 Input buffer No
HTQFP (PAP) 64 144 mm² 12 x 12
  • 14-Bit Resolution
  • 125-MSPS Sample Rate
  • High Signal-to-Noise Ratio (SNR):
    70.5 dBFS at 100 MHz fIN (TYP)
  • High Spurious-Free Dynamic Range (SFDR):
    82 dBc at 100-MHz fIN (TYP)
  • 2.3-VPP Differential Input Voltage
  • Internal Voltage Reference
  • 3.3-V Single-Supply Voltage
  • Analog Power Dissipation: 578 mW
    • Total Power Dissipation: 780 mW
  • Serial Programming Interface
  • TQFP-64 PowerPAD™ Package
  • SUPPORTS DEFENSE, AEROSPACE,
    AND MEDICAL APPLICATIONS
    • Controlled Baseline
    • One Assembly/Test Site
    • One Fabrication Site
    • Available in Military (–55.C/125°C)
      Temperature Range(1)
    • Extended Product Life Cycle
    • Extended Product-Change Notification
    • Product Traceability
  • APPLICATIONS
    • Wireless Communication
    • Test and Measurement Instrumentation
    • Single and Multichannel Digital Receivers
    • Communication Instrumentation
      • Radar, Infrared
    • Video and Imaging

(1)Custom temperature ranges available.

  • 14-Bit Resolution
  • 125-MSPS Sample Rate
  • High Signal-to-Noise Ratio (SNR):
    70.5 dBFS at 100 MHz fIN (TYP)
  • High Spurious-Free Dynamic Range (SFDR):
    82 dBc at 100-MHz fIN (TYP)
  • 2.3-VPP Differential Input Voltage
  • Internal Voltage Reference
  • 3.3-V Single-Supply Voltage
  • Analog Power Dissipation: 578 mW
    • Total Power Dissipation: 780 mW
  • Serial Programming Interface
  • TQFP-64 PowerPAD™ Package
  • SUPPORTS DEFENSE, AEROSPACE,
    AND MEDICAL APPLICATIONS
    • Controlled Baseline
    • One Assembly/Test Site
    • One Fabrication Site
    • Available in Military (–55.C/125°C)
      Temperature Range(1)
    • Extended Product Life Cycle
    • Extended Product-Change Notification
    • Product Traceability
  • APPLICATIONS
    • Wireless Communication
    • Test and Measurement Instrumentation
    • Single and Multichannel Digital Receivers
    • Communication Instrumentation
      • Radar, Infrared
    • Video and Imaging

(1)Custom temperature ranges available.

The ADS5500-EP is a high-performance, 14-bit, 125 MSPS analog-to-digital converter (ADC). To provide a complete converter solution, it includes a high-bandwidth linear sample-and-hold stage (S&H) and internal reference. Designed for applications demanding the highest speed and highest dynamic performance in a small space, the ADS5500-EP has excellent power consumption of 780 mW at 3.3-V single-supply voltage. This allows an even higher system integration density. The provided internal reference simplifies system design requirements. A parallel CMOS-compatible output ensures seamless interfacing with common logic.

The ADS5500-EP is available in a 64-pin TQFP PowerPAD package and is specified over the full temperature range of –55°C to +125°C.

The ADS5500-EP is a high-performance, 14-bit, 125 MSPS analog-to-digital converter (ADC). To provide a complete converter solution, it includes a high-bandwidth linear sample-and-hold stage (S&H) and internal reference. Designed for applications demanding the highest speed and highest dynamic performance in a small space, the ADS5500-EP has excellent power consumption of 780 mW at 3.3-V single-supply voltage. This allows an even higher system integration density. The provided internal reference simplifies system design requirements. A parallel CMOS-compatible output ensures seamless interfacing with common logic.

The ADS5500-EP is available in a 64-pin TQFP PowerPAD package and is specified over the full temperature range of –55°C to +125°C.

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重要文件 類型 標題 格式選項 日期
* Data sheet ADS5500-EP datasheet (Rev. C) 2008年 9月 2日
* VID ADS5500-EP VID V6205613 2016年 6月 21日
* Radiation & reliability report ADS5500MPAPEP Reliability Report 2015年 12月 18日
* Radiation & reliability report ADS5500MPAPREP Reliability Report 2011年 8月 25日
Application note Driving High-Speed ADCs: Circuit Topologies and System-Level Parameters (Rev. A) 2010年 9月 10日
Application note Smart Selection of ADC/DAC Enables Better Design of Software-Defined Radio 2009年 4月 28日
Application note CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital Converters 2008年 6月 8日
Application note Phase Noise Performance and Jitter Cleaning Ability of CDCE72010 2008年 6月 2日
User guide ADS5500/5541/5542/5520/5521/5522 14- and 12-Bit Single Channel ADC EVM (Rev. C) 2005年 9月 27日
Analog Design Journal 14-Bit, 125-MSPS ADS5500 Evaluation 2005年 1月 18日
Analog Design Journal Clocking High-Speed Data Converters 2005年 1月 18日
Application note Implementing a CDC7005 Low Jitter Clock Solution for HIgh Speed High IF ADC Dev 2004年 6月 25日
Product overview ADS5500 + CDC7005 Product Bulletin 2004年 6月 23日
Application note ADS5500, OPA695: PC Board Layout for Low Distortion High-Speed ADC Drivers 2004年 4月 22日
More literature Analogue-to-Digital Converters Support Multicarrier Systems 2004年 3月 2日

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