ADS42JB69

現行

雙通道、16 位元、250-MSPS 類比轉數位轉換器 (ADC)

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產品規格表

document-pdfAcrobat ADS42JBx9 Dual-Channel, 14- and 16-Bit, 250-MSPS Analog-to-Digital Converters datasheet (Rev. F) (英文) PDF | HTML

使用指南

document-pdfAcrobat
JESD204B Start Up: Configuration Requirements and Debug (英文)
document-pdfAcrobat
Understanding JESD204B Subclasses and Deterministic Latency (英文)

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ADC3668

現行

具有 LVDS 介面和高達 32768x 降取的 16 位元、雙通道、250MSPS ADC Lower power and LVDS interface

ADS42JB69

現行

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產品詳細資料

Sample rate (max) (Msps)

250

Resolution (Bits)

16

Number of input channels

2

Interface type

JESD204B

Analog input BW (MHz)

900

Features

High Performance

Rating

Catalog

Peak-to-peak input voltage range (V)

2.5

Power consumption (typ) (mW)

1700

Architecture

Pipeline

SNR (dB)

75.9

ENOB (Bits)

12.1

SFDR (dB)

95

Operating temperature range (°C)

-40 to 85

Input buffer

Yes

Sample rate (max) (Msps)

250

Resolution (Bits)

16

Number of input channels

2

Interface type

JESD204B

Analog input BW (MHz)

900

Features

High Performance

Rating

Catalog

Peak-to-peak input voltage range (V)

2.5

Power consumption (typ) (mW)

1700

Architecture

Pipeline

SNR (dB)

75.9

ENOB (Bits)

12.1

SFDR (dB)

95

Operating temperature range (°C)

-40 to 85

Input buffer

Yes

VQFN (RGC)

64

81 mm² (9 mm × 9 mm)

Dual-Channel ADCs
14- and 16-Bit Resolution
Maximum Clock Rate: 250 MSPS
JESD204B Serial Interface
- Subclass 0, 1, 2 Compliant
- Up to 3.125 Gbps
- Two and Four Lanes Support
Analog Input Buffer with High-Impedance Input
Flexible Input Clock Buffer:
Divide-by-1, -2, and -4
Differential Full-Scale Input: 2 V_PP and 2.5 V_PP
(Register Programmable)
Package: 9-mm × 9-mm VQFN-64
Power Dissipation: 850 mW/Ch
Aperture Jitter: 85 f_S rms
Internal Dither
Channel Isolation: 100 dB
Performance:
- f_IN = 170 MHz at 2 V_PP, –1 dBFS
  - SNR: 73.3 dBFS
  - SFDR: 93 dBc for HD2, HD3
  - SFDR: 100 dBc for Non HD2, HD3
- f_IN = 170 MHz at 2.5 V_PP, –1 dBFS
  - SNR: 74.7 dBFS
  - SFDR: 89 dBc for HD2, HD3 and
    95 dBc for Non HD2, HD3

Dual-Channel ADCs
14- and 16-Bit Resolution
Maximum Clock Rate: 250 MSPS
JESD204B Serial Interface
- Subclass 0, 1, 2 Compliant
- Up to 3.125 Gbps
- Two and Four Lanes Support
Analog Input Buffer with High-Impedance Input
Flexible Input Clock Buffer:
Divide-by-1, -2, and -4
Differential Full-Scale Input: 2 V_PP and 2.5 V_PP
(Register Programmable)
Package: 9-mm × 9-mm VQFN-64
Power Dissipation: 850 mW/Ch
Aperture Jitter: 85 f_S rms
Internal Dither
Channel Isolation: 100 dB
Performance:
- f_IN = 170 MHz at 2 V_PP, –1 dBFS
  - SNR: 73.3 dBFS
  - SFDR: 93 dBc for HD2, HD3
  - SFDR: 100 dBc for Non HD2, HD3
- f_IN = 170 MHz at 2.5 V_PP, –1 dBFS
  - SNR: 74.7 dBFS
  - SFDR: 89 dBc for HD2, HD3 and
    95 dBc for Non HD2, HD3

The ADS42JB69 and ADS42JB49 are high-linearity, dual-channel, 16- and 14-bit, 250-MSPS, analog-to-digital converters (ADCs). These devices support the JESD204B serial interface with data rates up to
3.125 Gbps. The buffered analog input provides uniform input impedance across a wide frequency range while minimizing sample-and-hold glitch energy making it easy to drive analog inputs up to very high input frequencies. A sampling clock divider allows more flexibility for system clock architecture design. The devices employ internal dither algorithms to provide excellent spurious-free dynamic range (SFDR) over a large input frequency range.

For all available packages, see the orderable addendum at the end of the datasheet.

The ADS42JB69 and ADS42JB49 are high-linearity, dual-channel, 16- and 14-bit, 250-MSPS, analog-to-digital converters (ADCs). These devices support the JESD204B serial interface with data rates up to
3.125 Gbps. The buffered analog input provides uniform input impedance across a wide frequency range while minimizing sample-and-hold glitch energy making it easy to drive analog inputs up to very high input frequencies. A sampling clock divider allows more flexibility for system clock architecture design. The devices employ internal dither algorithms to provide excellent spurious-free dynamic range (SFDR) over a large input frequency range.

For all available packages, see the orderable addendum at the end of the datasheet.

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重要文件	類型	標題	格式選項
*	資料表	ADS42JBx9 Dual-Channel, 14- and 16-Bit, 250-MSPS Analog-to-Digital Converters datasheet (Rev. F)	PDF \| HTML	2014/12/22
*	使用指南	JESD204B Start Up: Configuration Requirements and Debug		2012/10/26
*	使用指南	Understanding JESD204B Subclasses and Deterministic Latency		2012/10/26
	使用指南	TSW14J10 FMC-USB Interposer Card User's Guide (Rev. B)		2016/9/28
	應用說明	Correcting the Low-Frequency Response of the ADS42LBxx, ADS42JBxx for Time-Domai		2016/5/2
	使用指南	TSW14J50 User's Guide (Rev. A)		2016/4/25
	使用指南	TSW14J56 JESD204B High-Speed Data Capture/ Pattern Generator Card User's Guide (Rev. C)	PDF \| HTML	2016/1/11
	應用說明	Design Considerations for Avoiding Timing Errors during High-Speed ADC, LVDS Dat (Rev. A)		2015/5/22
	類比設計期刊	Analog Applications Journal 2Q 2015		2015/4/28
	類比設計期刊	JESD204B multi-device synchronization: Breaking down the requirements		2015/4/28
	白皮書	Ready to make the jump to JESD204B? White Paper (Rev. B)		2015/3/19
	使用指南	Interoperability of TI ADS42JB69 Family of JESD204B ADCs with Altera FPGAs		2013/10/4
	應用說明	Why Use Oversampling when Undersampling Can Do the Job? (Rev. A)		2013/7/19
	應用說明	LMK04828 as a Clock Source for the ADS42JB69		2012/11/14

設計與開發

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開發板

ADS42JB69EVM — ADS42JB69 雙通道、16 位元、250 MSPS 類比轉數位轉換器評估模組

The ADS42JB69EVM is an evaluation module (EVM) that allows for the evaluation of Texas Instruments’ ADS42JB69 and LMK04828 clock jitter cleaner. The ADS42JB69 is a low power, 16-bit, 250-MSPS analog to digital converter (ADC) with a buffered analog input and outputs featuring a JESD204B (...)

使用指南: PDF

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韌體

SLAC690 — TSW14J10EVM Xilinx Firmware Source

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韌體

TI204C-IP — Request for JESD204 rapid design IP

JESD204 快速設計 IP 被設計用於幫助 FPGA 工程師快速實現可運作的 JESD204 系統，從而加速開發過程。該 IP 的架構設計使得下游數位處理和其他應用邏輯能夠隔離於 JESD204 通訊協定的大多數性能和時序關鍵約束之外。該 IP 能夠幫助設計人員減少韌體開發時間並簡化 FPGA 的整合。

JESD204 快速設計 IP 無需權利金，用於 TI 高速資料轉換器。TI 將協助使用者配置初始連結，針對特定 FPGA 平台與 TI 資料轉換器 JMODE 之間的使用進行自訂。TI 將在 IP 測試完成並準備部署後，透過安全下載連結提供 IP。

JESD204 快速設計 IP 支援下列 (...)

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開發模組 (EVM) 的 GUI

DATACONVERTERPRO-SW — 高速資料轉換器 Pro GUI 安裝程式，v5.31

這款高速資料轉換器專業 GUI 是一款 PC（與 Windows® XP/7/10 相容）程式，旨在協助評估大多數 TI 高速資料轉換器 [類比轉數位轉換器 (ADC) 和數位轉類比轉換器 (DAC)] 和類比前端 (AFE) 平台。DATACONVERTERPRO-SW 旨在支援整個 TSW14xxx 系列資料擷取和模式產生卡，為時域和頻域中的資料轉換器分析提供強大且快速的解決方案，並支援單音、多音和調變訊號。此 GUI 也與 TI 模式產生 GUI 相容，可快速合成單音、多音和調變訊號。

使用者可以向 DATACONVERTERPRO-SW 提供自訂模式，以載入到 TI DAC。支援從 (...)

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開發模組 (EVM) 的 GUI