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數據轉換器
類比轉數位轉換器 (ADC)
高速 ADC (≥10 MSPS)

ADS54J64

現行

四通道、14 位元、1-GSPS、2x 超取樣類比轉數位轉換器 (ADC)

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產品規格表

ADS54J64

現行
產品規格表 立即訂購

產品詳細資料

Sample rate (max) (Msps) 500, 1000 Resolution (Bits) 14 Number of input channels 4 Interface type JESD204B Analog input BW (MHz) 1000 Features High Performance Rating Catalog Peak-to-peak input voltage range (V) 1.1 Power consumption (typ) (mW) 2500 Architecture Pipeline SNR (dB) 69 ENOB (Bits) 11.6 SFDR (dB) 86 Operating temperature range (°C) -40 to 85 Input buffer Yes
Sample rate (max) (Msps) 500, 1000 Resolution (Bits) 14 Number of input channels 4 Interface type JESD204B Analog input BW (MHz) 1000 Features High Performance Rating Catalog Peak-to-peak input voltage range (V) 1.1 Power consumption (typ) (mW) 2500 Architecture Pipeline SNR (dB) 69 ENOB (Bits) 11.6 SFDR (dB) 86 Operating temperature range (°C) -40 to 85 Input buffer Yes
VQFNP (RMP) 72 100 mm² 10 x 10
  • Quad Channel, 14-Bit Resolution
  • Maximum Sampling Rate: 1 GSPS
  • Maximum Output Sample Rate: 500 MSPS
  • High-Impedance Analog Input Buffer
  • Analog Input Bandwidth (–3 dB): 1 GHz
  • Output Options:
    • Digital Down Conversion (DDC) Using 16-Bit NCO
    • DDC Bypass With Full Rate Output Up to 500 MSPS
  • Differential Full-Scale Input: 1.1 VPP
  • JESD204B Interface:
    • Subclass 1 Support
    • 1 Lane per ADC Up to 10 Gbps
    • Dedicated SYNC Pin for Pair of Channels
  • Support for Multi-Chip Synchronization
  • Spectral Performance:
    • fIN = 190-MHz IF at –1 dBFS:
      • SNR: 69 dBFS
      • NSD: –153 dBFS/Hz
      • SFDR: 86 dBc (HD2, HD3),
        95 dBFS (Non HD2, HD3)
    • fIN = 370-MHz IF at –3 dBFS:
      • SNR: 68.5 dBFS
      • NSD: –152.5 dBFS/Hz
      • SFDR: 80 dBc (HD2, HD3),
        86 dBFS (Non HD2, HD3)
  • 72-Pin VQFN Package (10 mm × 10 mm)
  • Power Consumption: 625 mW/Ch, 2.5 W Total
  • Power Supplies: 1.15 V, 1.15 V, 1.9 V
  • Quad Channel, 14-Bit Resolution
  • Maximum Sampling Rate: 1 GSPS
  • Maximum Output Sample Rate: 500 MSPS
  • High-Impedance Analog Input Buffer
  • Analog Input Bandwidth (–3 dB): 1 GHz
  • Output Options:
    • Digital Down Conversion (DDC) Using 16-Bit NCO
    • DDC Bypass With Full Rate Output Up to 500 MSPS
  • Differential Full-Scale Input: 1.1 VPP
  • JESD204B Interface:
    • Subclass 1 Support
    • 1 Lane per ADC Up to 10 Gbps
    • Dedicated SYNC Pin for Pair of Channels
  • Support for Multi-Chip Synchronization
  • Spectral Performance:
    • fIN = 190-MHz IF at –1 dBFS:
      • SNR: 69 dBFS
      • NSD: –153 dBFS/Hz
      • SFDR: 86 dBc (HD2, HD3),
        95 dBFS (Non HD2, HD3)
    • fIN = 370-MHz IF at –3 dBFS:
      • SNR: 68.5 dBFS
      • NSD: –152.5 dBFS/Hz
      • SFDR: 80 dBc (HD2, HD3),
        86 dBFS (Non HD2, HD3)
  • 72-Pin VQFN Package (10 mm × 10 mm)
  • Power Consumption: 625 mW/Ch, 2.5 W Total
  • Power Supplies: 1.15 V, 1.15 V, 1.9 V

The ADS54J64 device is a quad-channel, 14-bit,
1-GSPS, analog-to-digital converter (ADC) offering wide-bandwidth, 2x oversampling and high SNR. The ADS54J64 supports a JESD204B serial interface with data rates up to 10 Gbps with one lane per channel. The buffered analog input provides uniform impedance across a wide frequency range and minimizes sample-and-hold glitch energy. The ADS54J64 provides excellent spurious-free dynamic range (SFDR) over a large input frequency range with very low power consumption. The digital signal processing block includes complex mixers followed by low-pass filters with decimate-by-2 and -4 options supporting up to a 200-MHz receive bandwidth. The ADS54J64 also supports a 14-bit, 500-MSPS output in DDC bypass mode.

A four-lane JESD204B interface simplifies connectivity, allowing high system integration density. An internal phase-locked loop (PLL) multiplies the incoming ADC sampling clock to derive the bit clock that is used to serialize the 14-bit data from each channel.

The ADS54J64 device is a quad-channel, 14-bit,
1-GSPS, analog-to-digital converter (ADC) offering wide-bandwidth, 2x oversampling and high SNR. The ADS54J64 supports a JESD204B serial interface with data rates up to 10 Gbps with one lane per channel. The buffered analog input provides uniform impedance across a wide frequency range and minimizes sample-and-hold glitch energy. The ADS54J64 provides excellent spurious-free dynamic range (SFDR) over a large input frequency range with very low power consumption. The digital signal processing block includes complex mixers followed by low-pass filters with decimate-by-2 and -4 options supporting up to a 200-MHz receive bandwidth. The ADS54J64 also supports a 14-bit, 500-MSPS output in DDC bypass mode.

A four-lane JESD204B interface simplifies connectivity, allowing high system integration density. An internal phase-locked loop (PLL) multiplies the incoming ADC sampling clock to derive the bit clock that is used to serialize the 14-bit data from each channel.
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* Data sheet ADS54J64 Quad-Channel, 14-Bit, 1-GSPS, 2x Oversampling, Analog-to-Digital Converter datasheet PDF | HTML 2017年 10月 9日

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ADS54J64EVM — ADS54J64 四通道 14 位元 1 GSPS、2 倍超取樣 ADC 評估模組

ADS54J64 評估模組 (EVM) 用於評估 ADS54J64 四通道、14 位元、1GSPS、2 倍超取樣類比轉數位轉換器 (ADC)。此 EVM 具有變壓器耦合類比輸入，可適應廣泛的訊號來源和頻率。此 EVM 的設計可直接連接至 TI 的各種資料擷取工具，包括 TSW14J56EVM 和 TSW14J50EVM。透過 ADS58J64EVM GUI 和高速資料轉換器專業級軟體 (DATACONVERTERPRO-SW) 分析工具提供額外支援。同時也提供 ADS54J64EVM 設計套件，其中包括電路圖、Gerber 及物料清單 (BOM)。

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TI204C-IP — Request for JESD204 rapid design IP

The JESD204 rapid design IP has been designed to enable FPGA engineers to achieve an accelerated path to a working JESD204 system. The IP has been architected in a way that downstream digital processing and other application logic are isolated from most of the performance- and timing-critical (...)

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DATACONVERTERPRO-SW — High Speed Data Converter Pro GUI Installer, v5.31

This high-speed data converter pro GUI is a PC (Windows® XP/7/10 compatible) program designed to aid in evaluation of most TI high-speed data converter [analog-to-digital converter (ADC) and digital-to-analog converter (DAC)] and analog front-end (AFE) platforms. Designed to support the entire (...)

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ADS54J64 IBIS Model

SBAM345.ZIP (38 KB) - IBIS Model
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ADS54J64 IBIS-AMI Model

SBAM344.ZIP (2273 KB) - IBIS-AMI Model
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計算工具

ANALOG-ENGINEER-CALC — PC software analog engineer's calculator

The analog engineer’s calculator is designed to speed up many of the repetitive calculations that analog circuit design engineers use on a regular basis. This PC-based tool provides a graphical interface with a list of various common calculations ranging from setting operational-amplifier (...)

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模擬工具

PSPICE-FOR-TI — PSpice® for TI 設計與模擬工具

PSpice® for TI 是有助於評估類比電路功能的設計和模擬環境。這款全功能設計和模擬套件使用 Cadence® 的類比分析引擎。PSpice for TI 包括業界最大的模型庫之一，涵蓋我們的類比和電源產品組合，以及特定類比行為模型，且使用無需支付費用。

PSpice for TI 設計和模擬環境可讓您使用其內建函式庫來模擬複雜的混合訊號設計。在進行佈局和製造之前，建立完整的終端設備設計和解決方案原型，進而縮短上市時間並降低開發成本。 

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