ADS54J64

現行

四通道、14 位元、1-GSPS、2x 超取樣類比轉數位轉換器 (ADC)

立即訂購

產品規格表

document-pdfAcrobat ADS54J64 Quad-Channel, 14-Bit, 1-GSPS, 2x Oversampling, Analog-to-Digital Converter datasheet (英文) PDF | HTML

ADS54J64

現行

產品規格表

立即訂購

產品詳細資料

Sample rate (max) (Msps)

500, 1000

Resolution (Bits)

14

Number of input channels

4

Interface type

JESD204B

Analog input BW (MHz)

1000

Features

High Performance

Rating

Catalog

Peak-to-peak input voltage range (V)

1.1

Power consumption (typ) (mW)

2500

Architecture

Pipeline

SNR (dB)

69

ENOB (Bits)

11.6

SFDR (dB)

86

Operating temperature range (°C)

-40 to 85

Input buffer

Yes

Sample rate (max) (Msps)

500, 1000

Resolution (Bits)

14

Number of input channels

4

Interface type

JESD204B

Analog input BW (MHz)

1000

Features

High Performance

Rating

Catalog

Peak-to-peak input voltage range (V)

1.1

Power consumption (typ) (mW)

2500

Architecture

Pipeline

SNR (dB)

69

ENOB (Bits)

11.6

SFDR (dB)

86

Operating temperature range (°C)

-40 to 85

Input buffer

Yes

VQFNP (RMP)

72

100 mm² (10 mm × 10 mm)

Quad Channel, 14-Bit Resolution
Maximum Sampling Rate: 1 GSPS
Maximum Output Sample Rate: 500 MSPS
High-Impedance Analog Input Buffer
Analog Input Bandwidth (–3 dB): 1 GHz
Output Options:
- Digital Down Conversion (DDC) Using 16-Bit NCO
- DDC Bypass With Full Rate Output Up to 500 MSPS
Differential Full-Scale Input: 1.1 V_PP
JESD204B Interface:
- Subclass 1 Support
- 1 Lane per ADC Up to 10 Gbps
- Dedicated SYNC Pin for Pair of Channels
Support for Multi-Chip Synchronization
Spectral Performance:
- f_IN = 190-MHz IF at –1 dBFS:
  - SNR: 69 dBFS
  - NSD: –153 dBFS/Hz
  - SFDR: 86 dBc (HD2, HD3),
    95 dBFS (Non HD2, HD3)
- f_IN = 370-MHz IF at –3 dBFS:
  - SNR: 68.5 dBFS
  - NSD: –152.5 dBFS/Hz
  - SFDR: 80 dBc (HD2, HD3),
    86 dBFS (Non HD2, HD3)
72-Pin VQFN Package (10 mm × 10 mm)
Power Consumption: 625 mW/Ch, 2.5 W Total
Power Supplies: 1.15 V, 1.15 V, 1.9 V

Quad Channel, 14-Bit Resolution
Maximum Sampling Rate: 1 GSPS
Maximum Output Sample Rate: 500 MSPS
High-Impedance Analog Input Buffer
Analog Input Bandwidth (–3 dB): 1 GHz
Output Options:
- Digital Down Conversion (DDC) Using 16-Bit NCO
- DDC Bypass With Full Rate Output Up to 500 MSPS
Differential Full-Scale Input: 1.1 V_PP
JESD204B Interface:
- Subclass 1 Support
- 1 Lane per ADC Up to 10 Gbps
- Dedicated SYNC Pin for Pair of Channels
Support for Multi-Chip Synchronization
Spectral Performance:
- f_IN = 190-MHz IF at –1 dBFS:
  - SNR: 69 dBFS
  - NSD: –153 dBFS/Hz
  - SFDR: 86 dBc (HD2, HD3),
    95 dBFS (Non HD2, HD3)
- f_IN = 370-MHz IF at –3 dBFS:
  - SNR: 68.5 dBFS
  - NSD: –152.5 dBFS/Hz
  - SFDR: 80 dBc (HD2, HD3),
    86 dBFS (Non HD2, HD3)
72-Pin VQFN Package (10 mm × 10 mm)
Power Consumption: 625 mW/Ch, 2.5 W Total
Power Supplies: 1.15 V, 1.15 V, 1.9 V

The ADS54J64 device is a quad-channel, 14-bit,
1-GSPS, analog-to-digital converter (ADC) offering wide-bandwidth, 2x oversampling and high SNR. The ADS54J64 supports a JESD204B serial interface with data rates up to 10 Gbps with one lane per channel. The buffered analog input provides uniform impedance across a wide frequency range and minimizes sample-and-hold glitch energy. The ADS54J64 provides excellent spurious-free dynamic range (SFDR) over a large input frequency range with very low power consumption. The digital signal processing block includes complex mixers followed by low-pass filters with decimate-by-2 and -4 options supporting up to a 200-MHz receive bandwidth. The ADS54J64 also supports a 14-bit, 500-MSPS output in DDC bypass mode.

A four-lane JESD204B interface simplifies connectivity, allowing high system integration density. An internal phase-locked loop (PLL) multiplies the incoming ADC sampling clock to derive the bit clock that is used to serialize the 14-bit data from each channel.

The ADS54J64 device is a quad-channel, 14-bit,
1-GSPS, analog-to-digital converter (ADC) offering wide-bandwidth, 2x oversampling and high SNR. The ADS54J64 supports a JESD204B serial interface with data rates up to 10 Gbps with one lane per channel. The buffered analog input provides uniform impedance across a wide frequency range and minimizes sample-and-hold glitch energy. The ADS54J64 provides excellent spurious-free dynamic range (SFDR) over a large input frequency range with very low power consumption. The digital signal processing block includes complex mixers followed by low-pass filters with decimate-by-2 and -4 options supporting up to a 200-MHz receive bandwidth. The ADS54J64 also supports a 14-bit, 500-MSPS output in DDC bypass mode.

A four-lane JESD204B interface simplifies connectivity, allowing high system integration density. An internal phase-locked loop (PLL) multiplies the incoming ADC sampling clock to derive the bit clock that is used to serialize the 14-bit data from each channel.

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重要文件	類型	標題	格式選項	下載最新的英文版本		日期
*	資料表	ADS54J64 Quad-Channel, 14-Bit, 1-GSPS, 2x Oversampling, Analog-to-Digital Converter datasheet	PDF \| HTML			2017/10/9

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