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放大器
運算放大器 (op amps)
高速運算放大器 (GBW ≥ 50 MHz)

OPA2607

現行

雙通道、低功耗精密 50-MHz 補償不全 CMOS 運算放大器

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OPA2607

現行
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產品詳細資料

Architecture FET / CMOS Input, Voltage FB Number of channels 2 Total supply voltage (+5 V = 5, ±5 V = 10) (min) (V) 2.2 Total supply voltage (+5 V = 5, ±5 V = 10) (max) (V) 5.5 GBW (typ) (MHz) 50 BW at Acl (MHz) 2.5 Acl, min spec gain (V/V) 6 Slew rate (typ) (V/µs) 24 Vn at flatband (typ) (nV√Hz) 3.8 Vn at 1 kHz (typ) (nV√Hz) 5.3 Iq per channel (typ) (mA) 0.9 Vos (offset voltage at 25°C) (max) (mV) 0.6 Rail-to-rail In to V-, Out Features Decompensated, Shutdown Rating Catalog Operating temperature range (°C) -40 to 125 CMRR (typ) (dB) 100 Input bias current (max) (pA) 10 Offset drift (typ) (µV/°C) 0.3 Iout (typ) (mA) 20 2nd harmonic (dBc) -105 3rd harmonic (dBc) -95 Frequency of harmonic distortion measurement (MHz) 0.02
Architecture FET / CMOS Input, Voltage FB Number of channels 2 Total supply voltage (+5 V = 5, ±5 V = 10) (min) (V) 2.2 Total supply voltage (+5 V = 5, ±5 V = 10) (max) (V) 5.5 GBW (typ) (MHz) 50 BW at Acl (MHz) 2.5 Acl, min spec gain (V/V) 6 Slew rate (typ) (V/µs) 24 Vn at flatband (typ) (nV√Hz) 3.8 Vn at 1 kHz (typ) (nV√Hz) 5.3 Iq per channel (typ) (mA) 0.9 Vos (offset voltage at 25°C) (max) (mV) 0.6 Rail-to-rail In to V-, Out Features Decompensated, Shutdown Rating Catalog Operating temperature range (°C) -40 to 125 CMRR (typ) (dB) 100 Input bias current (max) (pA) 10 Offset drift (typ) (µV/°C) 0.3 Iout (typ) (mA) 20 2nd harmonic (dBc) -105 3rd harmonic (dBc) -95 Frequency of harmonic distortion measurement (MHz) 0.02
SOIC (D) 8 29.4 mm² 4.9 x 6 VSSOP (DGK) 8 14.7 mm² 3 x 4.9 X2QFN (RUG) 10 3 mm² 1.5 x 2
  • Gain Bandwidth Product (GBW): 50 MHz
  • Quiescent Current: 900 µA (Typical)
  • Broadband Noise: 3.8 nV/√Hz
  • Input Offset Drift: 1.5 µV/°C (Maximum)
  • Offset Voltage: 120 µV (Typical)
  • Input Bias Current: 10 pA (Maximum)
  • Rail-to-Rail Output (RRO)
  • Decompensated, Gain ≥ 6 V/V (Stable)
  • Power Down Current: 1 µA (Maximum)
  • Supply Range: 2.2 V to 5.5 V
  • Gain Bandwidth Product (GBW): 50 MHz
  • Quiescent Current: 900 µA (Typical)
  • Broadband Noise: 3.8 nV/√Hz
  • Input Offset Drift: 1.5 µV/°C (Maximum)
  • Offset Voltage: 120 µV (Typical)
  • Input Bias Current: 10 pA (Maximum)
  • Rail-to-Rail Output (RRO)
  • Decompensated, Gain ≥ 6 V/V (Stable)
  • Power Down Current: 1 µA (Maximum)
  • Supply Range: 2.2 V to 5.5 V

The OPA607 and OPA2607 devices are decompensated, minimum gain of 6 V/V stable, general-purpose CMOS operational amplifier with low noise of 3.8 nV/√ Hz and a GBW of 50 MHz. The low noise and wide bandwidth of the OPAx607 devices make them attractive for general-purpose applications which require a good balance between cost and performance. The high-impedance CMOS inputs make the OPAx607 devices an ideal amplifier to interface with sensors with high output impedance (for example, piezoelectric transducers).

The OPAx607 devices feature a Power Down mode with a maximum quiescent current of less than 1 µA, making the device suitable for use in portable battery-powered applications. The rail-to-rail output (RRO) of the OPAx607 devices can swing up to 8 mV from the supply rails, maximizing dynamic range.

The OPAx607 is optimized for low supply voltage operation as low as 2.2 V (±1.1 V) and up to 5.5 V (±2.75 V), and is specified over the temperature range of –40°C to +125°C.

The OPA607 and OPA2607 devices are decompensated, minimum gain of 6 V/V stable, general-purpose CMOS operational amplifier with low noise of 3.8 nV/√ Hz and a GBW of 50 MHz. The low noise and wide bandwidth of the OPAx607 devices make them attractive for general-purpose applications which require a good balance between cost and performance. The high-impedance CMOS inputs make the OPAx607 devices an ideal amplifier to interface with sensors with high output impedance (for example, piezoelectric transducers).

The OPAx607 devices feature a Power Down mode with a maximum quiescent current of less than 1 µA, making the device suitable for use in portable battery-powered applications. The rail-to-rail output (RRO) of the OPAx607 devices can swing up to 8 mV from the supply rails, maximizing dynamic range.

The OPAx607 is optimized for low supply voltage operation as low as 2.2 V (±1.1 V) and up to 5.5 V (±2.75 V), and is specified over the temperature range of –40°C to +125°C.
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重要文件 類型 標題 格式選項 日期
* Data sheet OPAx607 50-MHz, Low-Power, Gain of 6-V/V Stable, Rail-to-Rail Output CMOS for Co datasheet (Rev. J) 2021年 4月 16日
Product overview High Speed Amplifiers for In-Vitro Diagnostics (IVD) Analog Front End PDF | HTML 2025年 4月 10日
Technical article 3 common questions when designing with high-speed amplifiers PDF | HTML 2020年 7月 17日
User guide DEM-OPA-SO-2A User's Guide (Rev. B) 2010年 4月 30日

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開發板

DEM-OPA-SO-2A — 適用於 SO-8 封裝的二路運算放大器評估模組

The DEM-OPA-SO-2A demonstration evaluation module helps designers evaluate the operation and performance of TI dual-channel, high-speed, wideband operational amplifiers. This unpopulated printed-circuit board (PCB) is compatible with products offered in the 8-lead SOIC (D) package.

For more (...)

使用指南: PDF
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計算工具

ANALOG-ENGINEER-CALC — PC software analog engineer's calculator

The analog engineer’s calculator is designed to speed up many of the repetitive calculations that analog circuit design engineers use on a regular basis. This PC-based tool provides a graphical interface with a list of various common calculations ranging from setting operational-amplifier (...)

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VOLT-DIVIDER-CALC — Voltage divider calculation tool

The voltage divider calculation tool (VOLT-DIVIDER-CALC) quickly determines a set of resistors for a voltage divider. This KnowledgeBase JavaScript utility can be used to find a set of resistors for a voltage divider to achieve the desired output voltage. VOLT-DIVIDER-CALC can also be used to (...)
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PSPICE-FOR-TI — PSpice® for TI 設計與模擬工具

PSpice® for TI 是有助於評估類比電路功能的設計和模擬環境。這款全功能設計和模擬套件使用 Cadence® 的類比分析引擎。PSpice for TI 包括業界最大的模型庫之一，涵蓋我們的類比和電源產品組合，以及特定類比行為模型，且使用無需支付費用。

PSpice for TI 設計和模擬環境可讓您使用其內建函式庫來模擬複雜的混合訊號設計。在進行佈局和製造之前，建立完整的終端設備設計和解決方案原型，進而縮短上市時間並降低開發成本。 

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TINA-TI provides all the conventional DC, transient and frequency domain analysis of SPICE and much more. TINA has extensive post-processing capability that allows you to format results the way you want them. Virtual instruments allow you to select input waveforms and probe circuit nodes voltages (...)
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參考設計

TIDA-010203 — 具 C2000 和 GaN 的 4-kW 單相圖騰柱 PFC 參考設計

此參考設計為具有 F280049/F280025 控制卡和 LMG342x EVM 電路板的 4-kW CCM 圖騰柱 PFC。此設計示範穩固的 PFC 解決方案，透過將控制器接地置於 MOSFET 腳的中間，以避免隔離式電流感測。得益於非隔離，AC 電流感測可透過高速放大器 OPA607 實作，有助於實現可靠的過電流保護。在此設計中，效率、熱影像、AC 壓降、照明突波與 EMI CE 皆經過完整驗證。透過已完成的測試資料，此參考設計可展現具有 C2000 和 GaN 的圖騰柱 PFC 的成熟度，是高效率產品 PFC 級設計的良好研究平台。
Design guide: PDF
電路圖: PDF
參考設計

TIDA-060019 — 高速電流分流監測器參考設計

此參考設計為使用高速放大器的低壓側、雙向電流分流監控器。此設計適用於可從以下方面受益的應用：更快速的故障偵測，單分流馬達控制，更高切換頻率，更高增益及或更低的一般 ADC 取樣雜訊。此設計採用 OPA365-Q1、OPA2836-Q1 和 OPA607，以 10 V/V 增益監控 1-mΩ 分流。預設配置適用於 ≤45-A 系統，可在 2.2 V 至 5.5 V 的 Vcc 範圍內準確感測最高 ±50x Vcc 的暫態電壓。預設配置在大多數 TI 馬達微控制器的 3.3-V、12 位元內部 ADC 一般擷取週期內可實現 <250 ns (...)
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封裝 針腳 CAD 符號、佔位空間與 3D 模型
SOIC (D) 8 Ultra Librarian
VSSOP (DGK) 8 Ultra Librarian
X2QFN (RUG) 10 Ultra Librarian
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