SPRUJD4A December 2024 – November 2025 AM62D-Q1
Some peripherals on the device include support for a debug suspend capability that allows the peripheral’s behavior to alter when an assigned CPU enters the debug suspend state. In order to use this feature, it must be enabled within the peripheral and a connection made between the desired suspend source (CPU) and the suspend destination (peripheral) of interest.
Details on the debug suspend feature for a specific peripheral, including how to enable it, is covered in the associated peripheral section.
On this device, there is a dedicated interrupt router (INTR) (DBGSUSPENDROUTER0 that supports the routing of a suspend source to a suspend destination. Details on the assignment of DBGSUSPENDROUTER0 inputs and outputs are provided .
| Index | Suspend Source | Description |
|---|---|---|
| 1 | A53SS0_0 | A53SS0 Core 0 |
| 2 | A53SS0_1 | A53SS0 Core 1 |
| 3 | A53SS0_2 | A53SS0 Core 2 |
| 4 | A53SS0_3 | A53SS0 Core 3 |
| 9 | C7X256V0 | C7x DSP / Deep Learning Acc. |
| 23 | WKUP_R5FSS | Device Management Cortex R5F |
| 24 | MCU_M4FSS | MCU M4F |
| 26 | SMS0_HSM | SMS HSM |
| Index | Suspend Destination | Description |
|---|---|---|
| 0 | WKUP_GTC0 | Global Time Counter |
| 1 | CPSW0 | Ethernet Switch (SoC) |
| 2 | DMSS | DMA SS (SoC) |
| 3 | DMSS_HSM | SA3SS DMSS_HSM |
| 4 | DMSS_CSI | DMA SS (CSI-RX) |
| 7-5 | Reserved | Reserved |
| 8 | TIMER0 | Dual Mode Timer (Main) |
| 9 | TIMER1 | |
| 10 | TIMER2 | |
| 11 | TIMER3 | |
| 12 | TIMER4 | |
| 13 | TIMER5 | |
| 14 | TIMER6 | |
| 15 | TIMER7 | |
| 16 | MCU_TIMER0 | Dual Mode Timer (MCU) |
| 17 | MCU_TIMER1 | |
| 18 | MCU_TIMER2 | |
| 19 | MCU_TIMER3 | |
| 20 | Reserved | Reserved |
| 21 | WKUP_TIMER0 | Dual Mode Timer (Wakeup) |
| 22 | WKUP_TIMER1 | |
| 23 | Reserved | Reserved |
| 24 | EPWM0 | Enhanced PWM (Main) |
| 25 | EPWM1 | |
| 26 | EPWM2 | |
| 27 | Reserved | Reserved |
| 28 | MCAN0 | MCAN (Main) |
| 29 | MCU_MCAN0 | MCAN (MCU) |
| 30 | MCU_MCAN1 | |
| 31 | Reserved | Reserved |
| 32 | MCRC64_0 | CRC (Main) |
| 33 | MCU_MCRC64_1 | CRC (MCU) |
| 34 | Reserved | Reserved |
| 35 | I2C0 | I2C (Main) |
| 36 | I2C1 | |
| 37 | I2C2 | |
| 38 | I2C3 | |
| 39 | MCU_I2C0 | I2C (MCU) |
| 40 | WKUP_I2C0 | I2C (Wakeup) |
| 41 | Reserved | Reserved |
| 42 | ECAP0 | ECAP (Main) |
| 43 | ECAP1 | |
| 44 | ECAP2 | |
| 45 | EQEP0 | EQEP (Main) |
| 46 | EQEP1 | |
| 47 | EQEP2 | |
| 49-48 | Reserved | Reserved |
| 50 | PDMA0 | Peripheral DMA |
| 51 | PDMA1 | |
| 52 | PDMA2 | |
| 53 | Reserved | Reserved |
| 54 | RTI2 | Real-time Interrupt (A53) |
| 55 | RTI3 | |
| 56 | RTI0 | |
| 57 | RTI1 | |
| 58 | RTI4 | Real-time Interrupt (C71) |
| 59 | MCU_RTI0 | Real-time Interrupt (MCU) |
| 60 | WKUP_RTI0 | Real-time Interrupt (DM) |
| 127-61 | Reserved | Reserved |