Packets are received on three ports, two Ethernet
port and one CPPI host port. Received packets have a received packet priority (0 to
7, with 7 being the highest priority).
The received packet priority is determined as follows:
- If the first packet LTYPE = VLAN_LTYPE_SEL then the received packet priority is the packet priority (VLAN tagged and priority tagged packets).
- Else if the first packet LTYPE = 0x0800 and byte
14 (following the LTYPE) is equal to 0x4X, and DSCP_IPV4_EN is set in
CPSW3_CPSW_NU_CPSW_NU_CPPI_P0_CONTROL_REG or
CPSW3_CPSW_NU_CPSW_NU_ETH_MAC_i_PN_CONTROL_REG, then the received packet
priority is the 6-bit TOS field in byte 15 (upper 6 bits) mapped through the
port’s DSCP priority mapping registers (IPv4 packet).
- Else if the first packet LTYPE = 0x86DD and the
most significant nibble of byte 14 (following the LTYPE) is equal to 0x6, and
DSCP_IPV6_EN is set in CPSW3_CPSW_NU_CPSW_NU_CPPI_P0_CONTROL_REG or
CPSW3_CPSW_NU_CPSW_NU_ETH_MAC_i_PN_CONTROL_REG, then the received packet
priority is the 6-bit priority (in the 6-bits following the upper nibble 0x6)
mapped through the port’s DSCP priority mapping registers (IPv6 packet).
- Else the received packet priority is the source (ingress) port priority.
The received packet priority is mapped through the
receive ports associated packet-priority-to-header-packet-priority-mapping register
(CPSW3_CPSW_NU_CPSW_NU_ETH_MAC_i_PN_RX_PRI_MAP_REG) to obtain the header packet
priority. The header packet priority is the hardware switch priority. The header
packet priority is also used as the actual transmit packet priority if the VLAN
information is to be sent on egress.
The header packet priority is mapped at each
destination FIFO through the CPSW3_CPSW_NU_CPSW_NU_ETH_MAC_i_PN_TX_PRI_MAP_REG
register (header priority to switch priority mapping register) to obtain the
hardware switch priority (hardware queue 0 through 7).