SPRUJD4A December 2024 – November 2025 AM62D-Q1
VBUS read accesses to RTC are satisfied from the Shadow MMR register bank. VBUS write accesses to RTC have their write data written to the Write Pending MMR register bank.
On Domain MMRs have their register values synchronized from the Write Pending MMR register bank to the Shadow MMRs and to the On Domain MMRs. Their value is synchronized into both of the alternate register banks simultaneously. The exact time depends on O32K_OSC_DEP_EN as described.
Core Domain MMRs have no such synchronization behavior. Values written to the Core Domain MMRs have their Shadow MMR copy updated.