SPRUJD4A December 2024 – November 2025 AM62D-Q1
The time counter registers span multiple 32-bit words. In order to read the time counter in an atomically consistent fashion, the time counter must be read by reading RTC_SUB_S_CNT, then reading RTC_S_CNT_LSW, and finally RTC_S_CNT_MSW.
The behavior of reading the time counter registers in this way depends on the value of RTC_GENRAL_CTL.CNT_FMODE. If the freeze mode is disabled or does not include RTC_SUB_S_CNT, then short sub-second waits may be implemented by reading RTC_SUB_S_CNT in a loop. However, in this usage, the crystal compensation feature may cause repeated, missing, or unexpected sub-second count values. The configuration of RTC should be checked if the sub-second counter is expected to be a clean, rolling binary count value.