SPRUJD4A December 2024 – November 2025 AM62D-Q1
The Device Power-on-Reset (POR) is controlled by the external pin MCU_PORz. This pin is driven by an external (off-chip) "Power-Good" Circuit or Power Management IC (PMIC). The MCU_PORz pin should be held active LOW (0) during the entire power-up phase. The device should be held in reset until all power supplies are stable with an additional delay for the High Frequency Oscillator (HFOSC0) clock to stabilize.
The SoC is divided into two separate functional Reset Domains: MCU Reset Domain and MAIN Reset Domain (each containing specific processing cores and peripherals).
Both MCU and Main domains have independent Warm Reset MCU_RESETz & MAIN_RESETz_REQ pins. All MCU domain resets act as controller resets to the whole device, whereas Main domain resets only reset Main domain (MCU domain is reset isolated from all Main domain resets). The following section outlines the various resets coming from pins and software MMR bits and their behavior.
AM62Dx also supports Low Power & Deepsleep modes where parts of the device are switched-off through Power-Domain switches. To support these low power modes the device is partitioned so that only a small region is kept active (Wake-up) and the rest can be powered off through power-down switches.
Figure 6-13 illustrates the high-level reset domain partition.