SPRUJD4A December 2024 – November 2025 AM62D-Q1
In this case, SW clears AUX_32K_EN to enable the ana_osc32k_clk then initials the RTCs MMR.
Note, crystal can take time 1 to 2 Secs before it is locked on 32768 Hz. SW needs to wait until this happens before it initializes the RTCs MMR to insure clock is stable and time will advance correctly. SW can/should verify the accuracy of time and adjust if required.
The switch is 1-time event per power up of ON domain.
Also Write 1 to RTC_GENRAL_CTL.O32K_OSC_DEP_EN since this clock needs to be active.