SPRUJD4A December 2024 – November 2025 AM62D-Q1
The following sections describe a high-level description of the different power modes of the device. Specific values are detailed in the device-specific data sheet. Note that not all modes are supported by software packages supplied by Texas Instruments.
| Low Power Modes | Wakeup Sources | Application State and Use Case |
|---|---|---|
| Partial IO | CANUART I/O Bank pins | The entire SoC is OFF except I/O pins in CANUART I/O Bank to maintain I/O wakeup capability from CANUART I/O Bank I/O pins. |
| Low Power Modes | Voltage Domain | Power Domain | Clocks | DDR | |||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| VDD_CORE / VDDR_CORE | VDDS_DDR | 1.8 Analog Rails | 1.8V/3.3V I/O Rails | GP_Core_CTL | PD_ICSSM | PD_CPSW | PD_A53_cluster_0 | PD_A53_x | PD_GPU | PD_DSS | GP_Core_CTL_MCU | Main OSC | DPLLs | ||
| Partial IO | OFF | OFF | OFF | Partial On | OFF | OFF | OFF | OFF | OFF | OFF | OFF | OFF | OFF | OFF | OFF |