SPRUJD4A December 2024 – November 2025 AM62D-Q1
| Instance | MAIN | MCU | WKUP |
|---|---|---|---|
| C7X256V0_CORE0 | ✓ |
| Module Instance | Power Sleep Controller | Power Domain | Module Domain | Index | Default | Controllable | Dependencies |
|---|---|---|---|---|---|---|---|
| C7X256V0_CORE0 | PSC0 | PD_C7x | LPSC_C7x_common | 57 | OFF | YES | LPSC_main_IP |
| Module Instance | Module Clock Input | Source Clock | Source Control Register | Description |
|---|---|---|---|---|
| C7X256V0_CORE0 | DIVH_CLK2_SOC_GCLK | C7X256V0_CLK (INSTANCE) | None | |
| C7X256V0_CORE0 | DIVH_CLK4_GCLK | C7X256V0_CLK (INSTANCE) | None | |
| C7X256V0_CORE0 | DIVH_CLK4_SOC_GCLK | C7X256V0_CLK (INSTANCE) | None | |
| C7X256V0_CORE0 | DIVP_CLK1_GCLK | C7X256V0_CLK (INSTANCE) | None | |
| C7X256V0_CORE0 | DIVP_CLK1_SOC_GCLK | C7X256V0_CLK (INSTANCE) | None |
| Module Instance | Source | Description |
|---|---|---|
| C7X256V0_CORE0 | PSC0 | C7X256V0_CORE0 reset |