SPRUJD4A December 2024 – November 2025 AM62D-Q1
CT-TBR System Interface Control This register provides control and status for the system interface of the CT-TBR
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| Instance Name | Physical Address |
|---|---|
| DEBUGSS0 | 0007 3C02 5104h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED1 | |||||||
| R/W | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED1 | |||||||
| R/W | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED1 | |||||||
| R/W | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED1 | IDLE_MODE | RESERVED | ERR | REQ_PEND | DATA_WIDTH | ||
| R/W | R/W | R | R/W | R | R/W | ||
| 0h | 3h | 0h | 0h | 1h | 0h | ||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:6 | RESERVED1 | R/W | 0h | |
| 5:4 | IDLE_MODE | R/W | 3h | This bit-field controls the idle behavior of the CT-TRB Read : Indicates the Idle modes outlined below Write 00b : Set Force-Idle. For CT-TBR, Force-Idle is identical to Smart-Idle Write 01b : Set No-Idle : The CT_TBR will acknowledge the idle request, but never transition to the idle state Write 10b : Set Smart-Idle : The CT-TBR uses the smart idle protocol. This is the default mode. Write 11b : Set Smart-Idle-Wkup : Since the CT-TBR does not support internal wakeup, this mode is identical to Smart-Idle |
| 3 | RESERVED | R | 0h | |
| 2 | ERR | R/W | 0h | This bit indicates that an access on the System Target I/F resulted in a error Read 0x0 : No errors since last clear Read 0x1 : At least one error condition on the I/F since last clear Write 0x0 : No effect Write 0x1 : Clears bit to 0 This bit clears to 0 when data acquisition is enabled (CTRL : ENBL 0- > 1) |
| 1 | REQ_PEND | R | 1h | This bit indicates if a read request is pending or active on the system interface Read 0x0 : No read requests pending or active Read 0x1 : A system initiator has posted a read request on the system interface and this request is pending or being serviced |
| 0 | DATA_WIDTH | R/W | 0h | This bit controls the supported access size for the system interface Read 0x0 : System interface will only support 32-bit reads Read 0x1 : System interface will only support 64-bit reads Write 0x0 : Set 32-bit mode Write 0x1 : Set 64-bit mode This bit is RO and set to 0 when synthesized for 32-bit data width |